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yosys/tests/opt/opt_rmdff_sat.ys

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Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder" This reverts commit c851dc13108021834533094a8a3236da6d9e0161, reversing changes made to f54bf1631ff37a83733c162e6ebd188c1d5ea18f.
2019-08-12 21:06:45 +02:00
read_verilog opt_rmdff_sat.v
Optimizing DFFs whose initial value prevents their value from changing This is a proof of concept implementation that invokes SAT solver via Pass::call method.
2019-05-28 08:48:21 +02:00
prep -flatten
opt_rmdff -sat
synth
Refactor "opt_rmdff -sat" Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-20 13:44:21 +02:00
select -assert-count 5 t:$_DFF_P_