yosys/tests/arch/xilinx/logic.ys

read_verilog ../common/logic.v
hierarchy -top top
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module

select -assert-count 1 t:INV
select -assert-count 6 t:LUT2
select -assert-count 2 t:LUT4
select -assert-none t:INV t:LUT2 t:LUT4 %% t:* %D
Share common tests 2019-10-18 12:19:59 +02:00			`read_verilog ../common/logic.v`
Add smoke tests to tests/xilinx 2019-09-10 07:08:03 +02:00			`hierarchy -top top`
hierarchy - proc reorder 2019-10-18 08:06:57 +02:00			`proc`
Make test without iopads 2019-12-28 16:22:24 +01:00			`equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check`
Add smoke tests to tests/xilinx 2019-09-10 07:08:03 +02:00			`design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)`
			`cd top # Constrain all select calls below inside the top module`

xilinx: Use INV instead of LUT1 when applicable 2019-11-24 14:17:46 +01:00			`select -assert-count 1 t:INV`
Add smoke tests to tests/xilinx 2019-09-10 07:08:03 +02:00			`select -assert-count 6 t:LUT2`
			`select -assert-count 2 t:LUT4`
Revert "Fix xilinx tests, when iopads are default" This reverts commit 477e43d921d204c6bc6403109fea6506802c948c. 2019-12-28 16:12:45 +01:00			`select -assert-none t:INV t:LUT2 t:LUT4 %% t:* %D`