yosys/tests/arch/common/mul.v

mirror of https://github.com/YosysHQ/yosys.git
module top
(
    input [5:0] x,
    input [5:0] y,

    output [11:0] A,
);
    assign A =  x * y;
endmodule
Add tests for ECP5 architecture 2019-09-03 10:53:37 +02:00			`module top`
			`(`
Unify verilog style 2019-10-18 12:50:24 +02:00			`input [5:0] x,`
			`input [5:0] y,`
Add tests for ECP5 architecture 2019-09-03 10:53:37 +02:00
Unify verilog style 2019-10-18 12:50:24 +02:00			`output [11:0] A,`
			`);`
			`assign A = x * y;`
Add tests for ECP5 architecture 2019-09-03 10:53:37 +02:00			`endmodule`