mirror of https://github.com/YosysHQ/yosys.git
11 lines
252 B
Verilog
11 lines
252 B
Verilog
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module dffsr_mixedpol(input CLK, D, CLEAR, PRESET, output reg Q, output QN);
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always @(posedge CLK, negedge CLEAR, posedge PRESET)
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if (PRESET) Q <= 1'b1;
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else if (~CLEAR) Q <= 1'b0;
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else Q <= ~D;
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assign QN = ~Q;
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endmodule
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