yosys/tests/various/setundef_selection_undriven.v

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module test;
    wire a;
    wire b;
endmodule
changed rtlil to verilog. setundef_selection_ff stays rtlil because we use specific cell names if write in verilog yosys assign name that can change 2026-03-09 01:14:03 +01:00			`module test;`
			`wire a;`
			`wire b;`
			`endmodule`