mirror of https://github.com/YosysHQ/yosys.git
21 lines
444 B
Plaintext
21 lines
444 B
Plaintext
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read_verilog <<EOT
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module foo(
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output o,
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input [0:0] i1,
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input i2
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);
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assign o = i1 ^ i2;
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endmodule
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EOT
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logger -expect log "wire width 1 input 2 \\i1" 1
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logger -expect log "wire input 3 \\i2" 1
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dump
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logger -check-expected
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write_verilog verilog_sbvector.out
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!grep -qF 'wire [0:0] i1;' verilog_sbvector.out
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!grep -qF 'input [0:0] i1;' verilog_sbvector.out
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!grep -qF 'wire i2;' verilog_sbvector.out
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!grep -qF 'input i2;' verilog_sbvector.out
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