mirror of https://github.com/YosysHQ/yosys.git
29 lines
809 B
Python
29 lines
809 B
Python
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from pyosys import libyosys as ys
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from pathlib import Path
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__file_dir__ = Path(__file__).absolute().parent
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def _dump_sigbit(bit):
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if bit.is_wire():
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if bit.wire.width == 1:
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return bit.wire.name.str()
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else:
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return f"{bit.wire.name} [{bit.offset}]"
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else:
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if bit.data == ys.State.S1:
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return 1
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elif bit.data == ys.State.S0:
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return 0
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else:
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assert "unknown constants not supported"
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d = ys.Design()
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ys.run_pass(f"read_verilog {__file_dir__ / 'spm.cut.v.gz'}", d)
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ys.run_pass(f"hierarchy -top spm", d)
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module = d.module(r"\spm")
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for conn_from, conn_to in module.connections_:
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for bit_from, bit_to in zip(conn_from, conn_to):
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print(f"assign {_dump_sigbit(bit_from)} = {_dump_sigbit(bit_to)};")
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