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yosys/techlibs/intel_alm/Makefile.inc

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synth_intel_alm: alternative synthesis for Intel FPGAs By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
2019-11-19 11:19:00 +01:00
OBJS += techlibs/intel_alm/synth_intel_alm.o
# Techmap
intel_alm: ABC9 sequential optimisations
2020-05-23 13:52:13 +02:00
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/abc9_map.v))
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/abc9_unmap.v))
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/abc9_model.v))
synth_intel_alm: alternative synthesis for Intel FPGAs By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
2019-11-19 11:19:00 +01:00
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/alm_map.v))
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/alm_sim.v))
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/arith_alm_map.v))
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/dff_map.v))
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/dff_sim.v))
intel_alm: DSP inference
2020-04-25 18:25:59 +02:00
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/dsp_sim.v))
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/dsp_map.v))
intel_alm: direct LUTRAM cell instantiation By instantiating the LUTRAM cell directly, we avoid a trip through altsyncram, which speeds up Quartus synthesis time. This also gives a little more flexibility, as Yosys can build RAMs out of individual 32x1 LUTRAM cells. While working on this, I discovered that the mem_init0 parameter of <family>_mlab_cell gets ignored by Quartus.
2020-04-16 13:24:04 +02:00
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/mem_sim.v))
intel_alm: Add IO buffer insertion Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 15:23:22 +02:00
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/misc_sim.v))
synth_intel_alm: alternative synthesis for Intel FPGAs By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
2019-11-19 11:19:00 +01:00
intel: move Cyclone V support to intel_alm
2020-07-27 15:21:05 +02:00
$(eval $(call add_share_file,share/intel_alm/cyclonev,techlibs/intel_alm/cyclonev/cells_sim.v))
synth_intel_alm: alternative synthesis for Intel FPGAs By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
2019-11-19 11:19:00 +01:00
# RAM
intel_alm: direct M10K instantiation This reverts commit a3a90f6377f251d3b6c5898eb1543f8832493bb8.
2020-07-26 20:28:10 +02:00
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m10k.txt))
intel_alm: M10K write-enable is negative-true
2022-03-09 17:40:32 +01:00
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m10k_map.v))
synth_intel_alm: alternative synthesis for Intel FPGAs By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
2019-11-19 11:19:00 +01:00
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/lutram_mlab.txt))
# Miscellaneous
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/megafunction_bb.v))