docs/source/code_examples/opt/opt_expr.ys

read_verilog <<EOT

module uut(
    input a,
    output y, z
);
    assign y = a == a;
    assign z = a != a;
endmodule

EOT

copy uut after
opt_expr after
clean

show -format dot -prefix opt_expr_full -notitle -color cornflowerblue uut
Docs: working on opt page 2024-01-17 11:00:42 +13:00			`read_verilog <<EOT`

			`module uut(`
			`input a,`
			`output y, z`
Remove trailing whitespaces 2026-06-23 07:24:59 +02:00			`);`
Docs: working on opt page 2024-01-17 11:00:42 +13:00			`assign y = a == a;`
			`assign z = a != a;`
			`endmodule`

			`EOT`

			`copy uut after`
			`opt_expr after`
			`clean`

			`show -format dot -prefix opt_expr_full -notitle -color cornflowerblue uut`