yosys/tests/verilog/local_include.v

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`include "temp_foo.v"
module top (input x, output y);
	foo bar (.a(x), .b(y));
endmodule
Add tests/verilog/local_include.* `read_verilog` supports checking both the current directory and the source directory for relative includes. Make sure we aren't regressing that. 2025-10-14 03:12:24 +02:00			`include "temp_foo.v"
			`module top (input x, output y);`
			`foo bar (.a(x), .b(y));`
			`endmodule`