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yosys/frontends/ast/simplify.cc

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initial import
2013-01-05 11:13:26 +01:00
/*
* yosys -- Yosys Open SYnthesis Suite
*
Fixing old e-mail addresses and deadnames s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
2021-06-08 00:39:36 +02:00
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
Fixed trailing whitespaces
2015-07-02 11:14:30 +02:00
*
initial import
2013-01-05 11:13:26 +01:00
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
Fixed trailing whitespaces
2015-07-02 11:14:30 +02:00
*
initial import
2013-01-05 11:13:26 +01:00
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* ---
*
* This is the AST frontend library.
*
* The AST frontend library is not a frontend on it's own but provides a
* generic abstract syntax tree (AST) abstraction for HDL code and can be
* used by HDL frontends. See "ast.h" for an overview of the API and the
* Verilog frontend for an usage example.
*
*/
#include "kernel/log.h"
Moved stand-alone libs to libs/ directory and added libs/subcircuit
2013-02-27 09:32:19 +01:00
#include "libs/sha1/sha1.h"
Added support for $readmemh/$readmemb
2014-10-26 20:33:10 +01:00
#include "frontends/verilog/verilog_frontend.h"
initial import
2013-01-05 11:13:26 +01:00
#include "ast.h"
#include <sstream>
#include <stdarg.h>
Added support for $readmemh/$readmemb
2014-10-26 20:33:10 +01:00
#include <stdlib.h>
Implemented basic real arithmetic
2014-06-14 08:51:22 +02:00
#include <math.h>
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
#include <optional>
simplify: std::gcd
2025-08-08 12:31:13 +02:00
#include <numeric>
initial import
2013-01-05 11:13:26 +01:00
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
2014-07-31 13:19:47 +02:00
YOSYS_NAMESPACE_BEGIN
initial import
2013-01-05 11:13:26 +01:00
using namespace AST;
using namespace AST_INTERNAL;
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
void AstNode::set_in_lvalue_flag(bool flag, bool no_descend)
{
if (flag != in_lvalue_from_above) {
in_lvalue_from_above = flag;
if (!no_descend)
fixup_hierarchy_flags();
}
}
void AstNode::set_in_param_flag(bool flag, bool no_descend)
{
if (flag != in_param_from_above) {
in_param_from_above = flag;
if (!no_descend)
fixup_hierarchy_flags();
}
}
void AstNode::fixup_hierarchy_flags(bool force_descend)
{
// With forced descend, we disable the implicit
// descend from within the set_* functions, instead
// we do an explicit descend at the end of this function
in_param = in_param_from_above;
switch (type) {
case AST_PARAMETER:
case AST_LOCALPARAM:
case AST_DEFPARAM:
case AST_PARASET:
case AST_PREFIX:
in_param = true;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : children)
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
child->set_in_param_flag(true, force_descend);
break;
case AST_REPLICATE:
case AST_WIRE:
case AST_GENIF:
case AST_GENCASE:
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : children)
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
child->set_in_param_flag(in_param, force_descend);
if (children.size() >= 1)
children[0]->set_in_param_flag(true, force_descend);
break;
case AST_GENFOR:
case AST_FOR:
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : children) {
log_assert((bool)child);
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
child->set_in_param_flag(in_param, force_descend);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
}
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
if (children.size() >= 2)
children[1]->set_in_param_flag(true, force_descend);
break;
default:
in_param = in_param_from_above;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : children)
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
child->set_in_param_flag(in_param, force_descend);
}
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& attr : attributes)
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
attr.second->set_in_param_flag(true, force_descend);
in_lvalue = in_lvalue_from_above;
switch (type) {
case AST_ASSIGN:
case AST_ASSIGN_EQ:
case AST_ASSIGN_LE:
if (children.size() >= 1)
children[0]->set_in_lvalue_flag(true, force_descend);
if (children.size() >= 2)
children[1]->set_in_lvalue_flag(in_lvalue, force_descend);
break;
default:
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : children)
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
child->set_in_lvalue_flag(in_lvalue, force_descend);
}
if (force_descend) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : children)
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
child->fixup_hierarchy_flags(true);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& attr : attributes)
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
attr.second->fixup_hierarchy_flags(true);
}
}
ast: Add support for $sformatf system function Signed-off-by: David Shah <dave@ds0.me>
2020-01-19 22:15:51 +01:00
// Process a format string and arguments for $display, $write, $sprintf, etc
fmt: Allow non-constant $display calls in initial blocks These are useful for formal verification with SBY where they can be used to display solver chosen `rand const reg` signals and signals derived from those. The previous error message for non-constant initial $display statements is downgraded to a log message. Constant initial $display statements will be shown both during elaboration and become part of the RTLIL so that the `sim` output is complete.
2023-09-22 17:56:34 +02:00
Fmt AstNode::processFormat(int stage, bool sformat_like, int default_base, size_t first_arg_at, bool may_fail) {
ast: use new format string helpers.
2020-11-29 09:57:07 +01:00
std::vector<VerilogFmtArg> args;
for (size_t index = first_arg_at; index < children.size(); index++) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
AstNode *node_arg = children[index].get();
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (node_arg->simplify(true, stage, -1, false)) { }
ast: use new format string helpers.
2020-11-29 09:57:07 +01:00
VerilogFmtArg arg = {};
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
arg.filename = *location.begin.filename;
arg.first_line = location.begin.line;
fmt: format %t consistently at initial
2023-06-28 03:51:22 +02:00
if (node_arg->type == AST_CONSTANT && node_arg->is_string) {
ast: use new format string helpers.
2020-11-29 09:57:07 +01:00
arg.type = VerilogFmtArg::STRING;
arg.str = node_arg->bitsAsConst().decode_string();
// and in case this will be used as an argument...
arg.sig = node_arg->bitsAsConst();
arg.signed_ = false;
fmt: format %t consistently at initial
2023-06-28 03:51:22 +02:00
} else if (node_arg->type == AST_IDENTIFIER && node_arg->str == "$time") {
arg.type = VerilogFmtArg::TIME;
} else if (node_arg->type == AST_IDENTIFIER && node_arg->str == "$realtime") {
arg.type = VerilogFmtArg::TIME;
arg.realtime = true;
} else if (node_arg->type == AST_CONSTANT) {
ast: use new format string helpers.
2020-11-29 09:57:07 +01:00
arg.type = VerilogFmtArg::INTEGER;
arg.sig = node_arg->bitsAsConst();
arg.signed_ = node_arg->is_signed;
fmt: Allow non-constant $display calls in initial blocks These are useful for formal verification with SBY where they can be used to display solver chosen `rand const reg` signals and signals derived from those. The previous error message for non-constant initial $display statements is downgraded to a log message. Constant initial $display statements will be shown both during elaboration and become part of the RTLIL so that the `sim` output is complete.
2023-09-22 17:56:34 +02:00
} else if (may_fail) {
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
log_file_info(*location.begin.filename, location.begin.line, "Skipping system task `%s' with non-constant argument at position %zu.\n", str.c_str(), index + 1);
fmt: Allow non-constant $display calls in initial blocks These are useful for formal verification with SBY where they can be used to display solver chosen `rand const reg` signals and signals derived from those. The previous error message for non-constant initial $display statements is downgraded to a log message. Constant initial $display statements will be shown both during elaboration and become part of the RTLIL so that the `sim` output is complete.
2023-09-22 17:56:34 +02:00
return Fmt();
fmt: format %t consistently at initial
2023-06-28 03:51:22 +02:00
} else {
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
log_file_error(*location.begin.filename, location.begin.line, "Failed to evaluate system task `%s' with non-constant argument at position %zu.\n", str.c_str(), index + 1);
ast: Add support for $sformatf system function Signed-off-by: David Shah <dave@ds0.me>
2020-01-19 22:15:51 +01:00
}
ast: use new format string helpers.
2020-11-29 09:57:07 +01:00
args.push_back(arg);
ast: Add support for $sformatf system function Signed-off-by: David Shah <dave@ds0.me>
2020-01-19 22:15:51 +01:00
}
Add new `$check` cell to represent assertions with a message.
2024-01-11 10:39:28 +01:00
Fmt fmt;
ast: use new format string helpers.
2020-11-29 09:57:07 +01:00
fmt.parse_verilog(args, sformat_like, default_base, /*task_name=*/str, current_module->name);
return fmt;
}
ast: Add support for $sformatf system function Signed-off-by: David Shah <dave@ds0.me>
2020-01-19 22:15:51 +01:00
Implement SV structs.
2020-05-08 15:40:49 +02:00
void AstNode::annotateTypedEnums(AstNode *template_node)
{
//check if enum
if (template_node->attributes.count(ID::enum_type)) {
//get reference to enum node:
std::string enum_type = template_node->attributes[ID::enum_type]->str.c_str();
// log("enum_type=%s (count=%lu)\n", enum_type.c_str(), current_scope.count(enum_type));
// log("current scope:\n");
// for (auto &it : current_scope)
// log(" %s\n", it.first.c_str());
log_assert(current_scope.count(enum_type) == 1);
AstNode *enum_node = current_scope.at(enum_type);
log_assert(enum_node->type == AST_ENUM);
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (enum_node->simplify(true, 1, -1, false)) { }
Implement SV structs.
2020-05-08 15:40:49 +02:00
//get width from 1st enum item:
log_assert(enum_node->children.size() >= 1);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
AstNode *enum_item0 = enum_node->children[0].get();
Implement SV structs.
2020-05-08 15:40:49 +02:00
log_assert(enum_item0->type == AST_ENUM_ITEM);
int width;
if (!enum_item0->range_valid)
width = 1;
else if (enum_item0->range_swapped)
width = enum_item0->range_right - enum_item0->range_left + 1;
else
width = enum_item0->range_left - enum_item0->range_right + 1;
log_assert(width > 0);
//add declared enum items:
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& enum_item : enum_node->children){
Implement SV structs.
2020-05-08 15:40:49 +02:00
log_assert(enum_item->type == AST_ENUM_ITEM);
//get is_signed
bool is_signed;
if (enum_item->children.size() == 1){
is_signed = false;
} else if (enum_item->children.size() == 2){
log_assert(enum_item->children[1]->type == AST_RANGE);
is_signed = enum_item->children[1]->is_signed;
} else {
Fix printf formats
2023-11-11 15:29:43 +01:00
log_error("enum_item children size==%zu, expected 1 or 2 for %s (%s)\n",
(size_t) enum_item->children.size(),
Implement SV structs.
2020-05-08 15:40:49 +02:00
enum_item->str.c_str(), enum_node->str.c_str()
);
}
//start building attribute string
std::string enum_item_str = "\\enum_value_";
//get enum item value
if(enum_item->children[0]->type != AST_CONSTANT){
log_error("expected const, got %s for %s (%s)\n",
type2str(enum_item->children[0]->type).c_str(),
enum_item->str.c_str(), enum_node->str.c_str()
);
}
RTLIL::Const val = enum_item->children[0]->bitsAsConst(width, is_signed);
enum_item_str.append(val.as_string());
//set attribute for available val to enum item name mappings
neater errors, lost in the sauce of source
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set_attribute(enum_item_str.c_str(), mkconst_str(location, enum_item->str));
Implement SV structs.
2020-05-08 15:40:49 +02:00
}
}
}
neater errors, lost in the sauce of source
2025-06-18 18:05:48 +02:00
static std::unique_ptr<AstNode> make_range(AstSrcLocType loc, int left, int right, bool is_signed = false)
Implement SV structs.
2020-05-08 15:40:49 +02:00
{
// generate a pre-validated range node for a fixed signal range.
neater errors, lost in the sauce of source
2025-06-18 18:05:48 +02:00
auto range = std::make_unique<AstNode>(loc, AST_RANGE);
Implement SV structs.
2020-05-08 15:40:49 +02:00
range->range_left = left;
range->range_right = right;
range->range_valid = true;
neater errors, lost in the sauce of source
2025-06-18 18:05:48 +02:00
range->children.push_back(AstNode::mkconst_int(loc, left, true));
range->children.push_back(AstNode::mkconst_int(loc, right, true));
Implement SV structs.
2020-05-08 15:40:49 +02:00
range->is_signed = is_signed;
return range;
}
Support packed arrays in struct/union.
2020-06-07 19:28:45 +02:00
static int range_width(AstNode *node, AstNode *rnode)
{
log_assert(rnode->type==AST_RANGE);
if (!rnode->range_valid) {
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
node->input_error("Non-constant range in declaration of %s\n", node->str.c_str());
Support packed arrays in struct/union.
2020-06-07 19:28:45 +02:00
}
// note: range swapping has already been checked for
return rnode->range_left - rnode->range_right + 1;
}
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
static int add_dimension(AstNode *node, AstNode *rnode)
Support for arrays with swapped ranges within structs This also corrects the implementation of C type arrays within structs. Fixes #3550
2022-11-12 08:48:25 +01:00
{
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
int width = range_width(node, rnode);
node->dimensions.push_back({ rnode->range_right, width, rnode->range_swapped });
return width;
Handle range offsets in packed arrays within packed structs This brings the metadata for packed arrays in packed structs in line with the metadata for unpacked arrays, and correctly handles the case when both lsb and msb in an address range are non-zero.
2023-02-05 11:01:37 +01:00
}
Support for arrays with swapped ranges within structs This also corrects the implementation of C type arrays within structs. Fixes #3550
2022-11-12 08:48:25 +01:00
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
[[noreturn]] static void struct_array_packing_error(AstNode *node)
Handle range offsets in packed arrays within packed structs This brings the metadata for packed arrays in packed structs in line with the metadata for unpacked arrays, and correctly handles the case when both lsb and msb in an address range are non-zero.
2023-02-05 11:01:37 +01:00
{
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
node->input_error("Unpacked array in packed struct/union member %s\n", node->str.c_str());
Support for arrays with swapped ranges within structs This also corrects the implementation of C type arrays within structs. Fixes #3550
2022-11-12 08:48:25 +01:00
}
Support packed arrays in struct/union.
2020-06-07 19:28:45 +02:00
static int size_packed_struct(AstNode *snode, int base_offset)
Generalise structs and add support for packed unions.
2020-05-12 15:25:33 +02:00
{
// Struct members will be laid out in the structure contiguously from left to right.
// Union members all have zero offset from the start of the union.
// Determine total packed size and assign offsets. Store these in the member node.
bool is_union = (snode->type == AST_UNION);
int offset = 0;
int packed_width = -1;
// examine members from last to first
for (auto it = snode->children.rbegin(); it != snode->children.rend(); ++it) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto node = it->get();
Generalise structs and add support for packed unions.
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int width;
if (node->type == AST_STRUCT || node->type == AST_UNION) {
// embedded struct or union
width = size_packed_struct(node, base_offset + offset);
}
else {
log_assert(node->type == AST_STRUCT_ITEM);
Support packed arrays in struct/union.
2020-06-07 19:28:45 +02:00
if (node->children.size() > 0 && node->children[0]->type == AST_RANGE) {
// member width e.g. bit [7:0] a
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
width = range_width(node, node->children[0].get());
Support packed arrays in struct/union.
2020-06-07 19:28:45 +02:00
if (node->children.size() == 2) {
Check for all cases of currently unsupported array dimensions in packed structs
2022-11-30 20:04:45 +01:00
// Unpacked array. Note that this is a Yosys extension; only packed data types
// and integer data types are allowed in packed structs / unions in SystemVerilog.
Support packed arrays in struct/union.
2020-06-07 19:28:45 +02:00
if (node->children[1]->type == AST_RANGE) {
Check for all cases of currently unsupported array dimensions in packed structs
2022-11-30 20:04:45 +01:00
// Unpacked array, e.g. bit [63:0] a [0:3]
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
// Pretend it's declared as a packed array, e.g. bit [0:3][63:0] a
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto rnode = node->children[1].get();
Handle range offsets in packed arrays within packed structs This brings the metadata for packed arrays in packed structs in line with the metadata for unpacked arrays, and correctly handles the case when both lsb and msb in an address range are non-zero.
2023-02-05 11:01:37 +01:00
if (rnode->children.size() == 1) {
// C-style array size, e.g. bit [63:0] a [4]
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
node->dimensions.push_back({ 0, rnode->range_left, true });
Handle range offsets in packed arrays within packed structs This brings the metadata for packed arrays in packed structs in line with the metadata for unpacked arrays, and correctly handles the case when both lsb and msb in an address range are non-zero.
2023-02-05 11:01:37 +01:00
width *= rnode->range_left;
} else {
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
width *= add_dimension(node, rnode);
Handle range offsets in packed arrays within packed structs This brings the metadata for packed arrays in packed structs in line with the metadata for unpacked arrays, and correctly handles the case when both lsb and msb in an address range are non-zero.
2023-02-05 11:01:37 +01:00
}
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
add_dimension(node, node->children[0].get());
Support packed arrays in struct/union.
2020-06-07 19:28:45 +02:00
}
else {
Support for packed multidimensional arrays within packed structs
2022-12-03 19:54:47 +01:00
// The Yosys extension for unpacked arrays in packed structs / unions
// only supports memories, i.e. e.g. logic [7:0] a [256] - see above.
struct_array_packing_error(node);
Support packed arrays in struct/union.
2020-06-07 19:28:45 +02:00
}
Support for arrays with swapped ranges within structs This also corrects the implementation of C type arrays within structs. Fixes #3550
2022-11-12 08:48:25 +01:00
} else {
Support for packed multidimensional arrays within packed structs
2022-12-03 19:54:47 +01:00
// Vector
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
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add_dimension(node, node->children[0].get());
Support packed arrays in struct/union.
2020-06-07 19:28:45 +02:00
}
// range nodes are now redundant
node->children.clear();
}
Check for all cases of currently unsupported array dimensions in packed structs
2022-11-30 20:04:45 +01:00
else if (node->children.size() > 0 && node->children[0]->type == AST_MULTIRANGE) {
Support for packed multidimensional arrays within packed structs
2022-12-03 19:54:47 +01:00
// Packed array, e.g. bit [3:0][63:0] a
if (node->children.size() != 1) {
// The Yosys extension for unpacked arrays in packed structs / unions
// only supports memories, i.e. e.g. logic [7:0] a [256] - see above.
struct_array_packing_error(node);
}
width = 1;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
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for (auto& rnode : node->children[0]->children) {
width *= add_dimension(node, rnode.get());
Support packed arrays in struct/union.
2020-06-07 19:28:45 +02:00
}
Generalise structs and add support for packed unions.
2020-05-12 15:25:33 +02:00
// range nodes are now redundant
node->children.clear();
}
else if (node->range_left < 0) {
// 1 bit signal: bit, logic or reg
width = 1;
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
node->dimensions.push_back({ 0, width, false });
Generalise structs and add support for packed unions.
2020-05-12 15:25:33 +02:00
}
else {
// already resolved and compacted
width = node->range_left - node->range_right + 1;
}
if (is_union) {
node->range_right = base_offset;
node->range_left = base_offset + width - 1;
}
else {
node->range_right = base_offset + offset;
node->range_left = base_offset + offset + width - 1;
}
node->range_valid = true;
}
if (is_union) {
// check that all members have the same size
if (packed_width == -1) {
// first member
packed_width = width;
}
else {
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
if (packed_width != width)
node->input_error("member %s of a packed union has %d bits, expecting %d\n", node->str.c_str(), width, packed_width);
Generalise structs and add support for packed unions.
2020-05-12 15:25:33 +02:00
}
}
else {
offset += width;
}
}
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
int width = is_union ? packed_width : offset;
snode->range_right = base_offset;
snode->range_left = base_offset + width - 1;
snode->range_valid = true;
Resolve struct member multiple dimensions defined in stages with typedef
2024-01-05 19:29:06 +01:00
snode->dimensions.push_back({ 0, width, false });
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
return width;
Support packed arrays in struct/union.
2020-06-07 19:28:45 +02:00
}
neater errors, lost in the sauce of source
2025-06-18 18:05:48 +02:00
static std::unique_ptr<AstNode> node_int(AstSrcLocType loc, int ival)
Support packed arrays in struct/union.
2020-06-07 19:28:45 +02:00
{
neater errors, lost in the sauce of source
2025-06-18 18:05:48 +02:00
return AstNode::mkconst_int(loc, ival, true);
Support packed arrays in struct/union.
2020-06-07 19:28:45 +02:00
}
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
static std::unique_ptr<AstNode> multiply_by_const(std::unique_ptr<AstNode> expr_node, int stride)
Support 2D bit arrays in structures. Optimise array indexing.
2020-06-08 21:34:52 +02:00
{
neater errors, lost in the sauce of source
2025-06-18 18:05:48 +02:00
auto loc = expr_node->location;
return std::make_unique<AstNode>(loc, AST_MUL, std::move(expr_node), node_int(loc, stride));
Support 2D bit arrays in structures. Optimise array indexing.
2020-06-08 21:34:52 +02:00
}
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
static std::unique_ptr<AstNode> normalize_index(AstNode *expr, AstNode *decl_node, int dimension)
Support 2D bit arrays in structures. Optimise array indexing.
2020-06-08 21:34:52 +02:00
{
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto new_expr = expr->clone();
neater errors, lost in the sauce of source
2025-06-18 18:05:48 +02:00
auto loc = expr->location;
Made make_struct_member_range side-effect-free again
2022-12-04 06:54:22 +01:00
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
int offset = decl_node->dimensions[dimension].range_right;
Handle range offsets in packed arrays within packed structs This brings the metadata for packed arrays in packed structs in line with the metadata for unpacked arrays, and correctly handles the case when both lsb and msb in an address range are non-zero.
2023-02-05 11:01:37 +01:00
if (offset) {
neater errors, lost in the sauce of source
2025-06-18 18:05:48 +02:00
new_expr = std::make_unique<AstNode>(loc, AST_SUB, std::move(new_expr), node_int(loc, offset));
Handle range offsets in packed arrays within packed structs This brings the metadata for packed arrays in packed structs in line with the metadata for unpacked arrays, and correctly handles the case when both lsb and msb in an address range are non-zero.
2023-02-05 11:01:37 +01:00
}
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
// Packed dimensions are normally indexed by lsb, while unpacked dimensions are normally indexed by msb.
if ((dimension < decl_node->unpacked_dimensions) ^ decl_node->dimensions[dimension].range_swapped) {
// Swap the index if the dimension is declared the "wrong" way.
int left = decl_node->dimensions[dimension].range_width - 1;
neater errors, lost in the sauce of source
2025-06-18 18:05:48 +02:00
new_expr = std::make_unique<AstNode>(loc, AST_SUB, node_int(loc, left), std::move(new_expr));
Support for arrays with swapped ranges within structs This also corrects the implementation of C type arrays within structs. Fixes #3550
2022-11-12 08:48:25 +01:00
}
Made make_struct_member_range side-effect-free again
2022-12-04 06:54:22 +01:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
return new_expr;
Support for packed multidimensional arrays within packed structs
2022-12-03 19:54:47 +01:00
}
Support for arrays with swapped ranges within structs This also corrects the implementation of C type arrays within structs. Fixes #3550
2022-11-12 08:48:25 +01:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
static std::unique_ptr<AstNode> index_offset(std::unique_ptr<AstNode> offset, AstNode *rnode, AstNode *decl_node, int dimension, int &stride)
Support for packed multidimensional arrays within packed structs
2022-12-03 19:54:47 +01:00
{
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
stride /= decl_node->dimensions[dimension].range_width;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto right = normalize_index(rnode->children.back().get(), decl_node, dimension);
auto add_offset = stride > 1 ? multiply_by_const(std::move(right), stride) : std::move(right);
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
return offset ? std::make_unique<AstNode>(rnode->location, AST_ADD, std::move(offset), std::move(add_offset)) : std::move(add_offset);
Support 2D bit arrays in structures. Optimise array indexing.
2020-06-08 21:34:52 +02:00
}
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
static std::unique_ptr<AstNode> index_msb_offset(std::unique_ptr<AstNode> lsb_offset, AstNode *rnode, AstNode *decl_node, int dimension, int stride)
Support 2D bit arrays in structures. Optimise array indexing.
2020-06-08 21:34:52 +02:00
{
Support for packed multidimensional arrays within packed structs
2022-12-03 19:54:47 +01:00
log_assert(rnode->children.size() <= 2);
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto loc = rnode->location;
Support for packed multidimensional arrays within packed structs
2022-12-03 19:54:47 +01:00
// Offset to add to LSB
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
std::unique_ptr<AstNode> add_offset;
Support for packed multidimensional arrays within packed structs
2022-12-03 19:54:47 +01:00
if (rnode->children.size() == 1) {
// Index, e.g. s.a[i]
neater errors, lost in the sauce of source
2025-06-18 18:05:48 +02:00
add_offset = node_int(rnode->location, stride - 1);
Support for packed multidimensional arrays within packed structs
2022-12-03 19:54:47 +01:00
}
else {
// rnode->children.size() == 2
// Slice, e.g. s.a[i:j]
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto left = normalize_index(rnode->children[0].get(), decl_node, dimension);
auto right = normalize_index(rnode->children[1].get(), decl_node, dimension);
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
add_offset = std::make_unique<AstNode>(loc, AST_SUB, std::move(left), std::move(right));
Made make_struct_member_range side-effect-free again
2022-12-04 06:54:22 +01:00
if (stride > 1) {
Support for packed multidimensional arrays within packed structs
2022-12-03 19:54:47 +01:00
// offset = (msb - lsb + 1)*stride - 1
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto slice_width = std::make_unique<AstNode>(loc, AST_ADD, std::move(add_offset), node_int(loc, 1));
add_offset = std::make_unique<AstNode>(loc, AST_SUB, multiply_by_const(std::move(slice_width), stride), node_int(loc, 1));
Support for swapped ranges in second array dimension
2022-11-23 16:31:08 +01:00
}
}
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
return std::make_unique<AstNode>(loc, AST_ADD, std::move(lsb_offset), std::move(add_offset));
Support packed arrays in struct/union.
2020-06-07 19:28:45 +02:00
}
Support 2D bit arrays in structures. Optimise array indexing.
2020-06-08 21:34:52 +02:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
std::unique_ptr<AstNode> AstNode::make_index_range(AstNode *decl_node, bool unpacked_range)
Support packed arrays in struct/union.
2020-06-07 19:28:45 +02:00
{
// Work out the range in the packed array that corresponds to a struct member
// taking into account any range operations applicable to the current node
// such as array indexing or slicing
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
if (children.empty()) {
Support packed arrays in struct/union.
2020-06-07 19:28:45 +02:00
// no range operations apply, return the whole width
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
return make_range(decl_node->location, decl_node->range_left - decl_node->range_right, 0);
Support packed arrays in struct/union.
2020-06-07 19:28:45 +02:00
}
Support for packed multidimensional arrays within packed structs
2022-12-03 19:54:47 +01:00
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
log_assert(children.size() == 1);
Support for packed multidimensional arrays within packed structs
2022-12-03 19:54:47 +01:00
// Range operations
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
AstNode *rnode = children[0].get();
std::unique_ptr<AstNode> offset = nullptr;
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
int dim = unpacked_range ? 0 : decl_node->unpacked_dimensions;
int max_dim = unpacked_range ? decl_node->unpacked_dimensions : GetSize(decl_node->dimensions);
int stride = 1;
for (int i = dim; i < max_dim; i++) {
stride *= decl_node->dimensions[i].range_width;
}
Support for packed multidimensional arrays within packed structs
2022-12-03 19:54:47 +01:00
// Calculate LSB offset for the final index / slice
if (rnode->type == AST_RANGE) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
offset = index_offset(std::move(offset), rnode, decl_node, dim, stride);
Support 2D bit arrays in structures. Optimise array indexing.
2020-06-08 21:34:52 +02:00
}
Support for packed multidimensional arrays within packed structs
2022-12-03 19:54:47 +01:00
else if (rnode->type == AST_MULTIRANGE) {
// Add offset for each dimension
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
AstNode *mrnode = rnode;
int stop_dim = std::min(GetSize(mrnode->children), max_dim);
for (; dim < stop_dim; dim++) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
rnode = mrnode->children[dim].get();
offset = index_offset(std::move(offset), rnode, decl_node, dim, stride);
Support for packed multidimensional arrays within packed structs
2022-12-03 19:54:47 +01:00
}
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
dim--; // Step back to the final index / slice
Support packed arrays in struct/union.
2020-06-07 19:28:45 +02:00
}
else {
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
input_error("Unsupported range operation for %s\n", str.c_str());
}
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
std::unique_ptr<AstNode> index_range = std::make_unique<AstNode>(rnode->location, AST_RANGE);
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
if (!unpacked_range && (stride > 1 || GetSize(rnode->children) == 2)) {
// Calculate MSB offset for the final index / slice of packed dimensions.
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
std::unique_ptr<AstNode>msb_offset = index_msb_offset(offset->clone(), rnode, decl_node, dim, stride);
index_range->children.push_back(std::move(msb_offset));
Support packed arrays in struct/union.
2020-06-07 19:28:45 +02:00
}
Support for packed multidimensional arrays within packed structs
2022-12-03 19:54:47 +01:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
index_range->children.push_back(std::move(offset));
Support for packed multidimensional arrays within packed structs
2022-12-03 19:54:47 +01:00
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
return index_range;
Support packed arrays in struct/union.
2020-06-07 19:28:45 +02:00
}
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
AstNode *AstNode::get_struct_member() const
Index struct/union members within corresponding wire chunks This guards against access to bits outside of struct/union members via dynamic indexing.
2023-02-28 18:45:55 +01:00
{
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
AstNode *member_node;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
if (attributes.count(ID::wiretype) && (member_node = attributes.at(ID::wiretype).get()) &&
(member_node->type == AST_STRUCT_ITEM || member_node->type == AST_STRUCT || member_node->type == AST_UNION))
Index struct/union members within corresponding wire chunks This guards against access to bits outside of struct/union members via dynamic indexing.
2023-02-28 18:45:55 +01:00
{
return member_node;
}
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
return nullptr;
Index struct/union members within corresponding wire chunks This guards against access to bits outside of struct/union members via dynamic indexing.
2023-02-28 18:45:55 +01:00
}
Generalise structs and add support for packed unions.
2020-05-12 15:25:33 +02:00
static void add_members_to_scope(AstNode *snode, std::string name)
{
// add all the members in a struct or union to local scope
// in case later referenced in assignments
log_assert(snode->type==AST_STRUCT || snode->type==AST_UNION);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto &node : snode->children) {
Fix access to whole sub-structs (#3086) * Add support for accessing whole struct * Update tests Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2022-02-14 14:34:20 +01:00
auto member_name = name + "." + node->str;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_scope[member_name] = node.get();
Generalise structs and add support for packed unions.
2020-05-12 15:25:33 +02:00
if (node->type != AST_STRUCT_ITEM) {
// embedded struct or union
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
add_members_to_scope(node.get(), name + "." + node->str);
Generalise structs and add support for packed unions.
2020-05-12 15:25:33 +02:00
}
}
}
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
std::unique_ptr<AstNode> make_packed_struct(AstNode *template_node, std::string &name, decltype(AstNode::attributes) &attributes)
Implement SV structs.
2020-05-08 15:40:49 +02:00
{
// create a wire for the packed struct
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto loc = template_node->location;
auto wnode = std::make_unique<AstNode>(loc, AST_WIRE, make_range(loc, template_node->range_left, 0));
Implement SV structs.
2020-05-08 15:40:49 +02:00
wnode->str = name;
wnode->is_logic = true;
wnode->range_valid = true;
Generalise structs and add support for packed unions.
2020-05-12 15:25:33 +02:00
wnode->is_signed = template_node->is_signed;
Handling of attributes for struct / union variables (* nowrshmsk *) on a struct / union variable now affects dynamic bit slice assignments to members of the struct / union. (* nowrshmsk *) can in some cases yield significant resource savings; the combination of pipeline shifting and indexed writes is an example of this. Constructs similar to the one below can benefit from (* nowrshmsk *), and in addition it is no longer necessary to split out the shift assignments on separate lines in order to avoid the error message "ERROR: incompatible mix of lookahead and non-lookahead IDs in LHS expression." always_ff @(posedge clk) begin if (rotate) begin { v5, v4, v3, v2, v1, v0 } <= { v4, v3, v2, v1, v0, v5 }; if (res) begin v0.bytes <= '0; end else if (w) begin v0.bytes[addr] <= data; end end end
2023-03-02 19:02:30 +01:00
for (auto &pair : attributes) {
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
wnode->set_attribute(pair.first, pair.second->clone());
Handling of attributes for struct / union variables (* nowrshmsk *) on a struct / union variable now affects dynamic bit slice assignments to members of the struct / union. (* nowrshmsk *) can in some cases yield significant resource savings; the combination of pipeline shifting and indexed writes is an example of this. Constructs similar to the one below can benefit from (* nowrshmsk *), and in addition it is no longer necessary to split out the shift assignments on separate lines in order to avoid the error message "ERROR: incompatible mix of lookahead and non-lookahead IDs in LHS expression." always_ff @(posedge clk) begin if (rotate) begin { v5, v4, v3, v2, v1, v0 } <= { v4, v3, v2, v1, v0, v5 }; if (res) begin v0.bytes <= '0; end else if (w) begin v0.bytes[addr] <= data; end end end
2023-03-02 19:02:30 +01:00
}
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
// resolve packed dimension
while (wnode->simplify(true, 1, -1, false)) {}
Implement SV structs.
2020-05-08 15:40:49 +02:00
// make sure this node is the one in scope for this name
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_scope[name] = wnode.get();
Generalise structs and add support for packed unions.
2020-05-12 15:25:33 +02:00
// add all the struct members to scope under the wire's name
add_members_to_scope(template_node, name);
Implement SV structs.
2020-05-08 15:40:49 +02:00
return wnode;
}
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
static void prepend_ranges(std::unique_ptr<AstNode> &range, AstNode *range_add)
Resolve multiple dimensions defined in stages with typedef
2024-01-01 01:18:00 +01:00
{
// Convert range to multirange.
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto loc = range->location;
Resolve multiple dimensions defined in stages with typedef
2024-01-01 01:18:00 +01:00
if (range->type == AST_RANGE)
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
range = std::make_unique<AstNode>(loc, AST_MULTIRANGE, std::move(range));
Resolve multiple dimensions defined in stages with typedef
2024-01-01 01:18:00 +01:00
// Add range or ranges.
if (range_add->type == AST_RANGE)
range->children.insert(range->children.begin(), range_add->clone());
else {
int i = 0;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : range_add->children)
Resolve multiple dimensions defined in stages with typedef
2024-01-01 01:18:00 +01:00
range->children.insert(range->children.begin() + i++, child->clone());
}
}
Avoid generating wires for function args which are constant
2020-07-25 05:18:24 +02:00
// check if a node or its children contains an assignment to the given variable
static bool node_contains_assignment_to(const AstNode* node, const AstNode* var)
{
if (node->type == AST_ASSIGN_EQ || node->type == AST_ASSIGN_LE) {
// current node is iteslf an assignment
log_assert(node->children.size() >= 2);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
const AstNode* lhs = node->children[0].get();
Avoid generating wires for function args which are constant
2020-07-25 05:18:24 +02:00
if (lhs->type == AST_IDENTIFIER && lhs->str == var->str)
return false;
}
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : node->children) {
Avoid generating wires for function args which are constant
2020-07-25 05:18:24 +02:00
// if this child shadows the given variable
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
if (child.get() != var && child->str == var->str && child->type == AST_WIRE)
Avoid generating wires for function args which are constant
2020-07-25 05:18:24 +02:00
break; // skip the remainder of this block/scope
// depth-first short circuit
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
if (!node_contains_assignment_to(child.get(), var))
Avoid generating wires for function args which are constant
2020-07-25 05:18:24 +02:00
return false;
}
return true;
}
verilog: significant block scoping improvements This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
2021-01-27 19:30:22 +01:00
static std::string prefix_id(const std::string &prefix, const std::string &str)
{
log_assert(!prefix.empty() && (prefix.front() == '$' || prefix.front() == '\\'));
log_assert(!str.empty() && (str.front() == '$' || str.front() == '\\'));
log_assert(prefix.back() == '.');
if (str.front() == '\\')
return prefix + str.substr(1);
return prefix + str;
}
verilog: use derived module info to elaborate cell connections - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
2021-10-20 02:46:26 +02:00
// direct access to this global should be limited to the following two functions
static const RTLIL::Design *simplify_design_context = nullptr;
void AST::set_simplify_design_context(const RTLIL::Design *design)
{
log_assert(!simplify_design_context || !design);
simplify_design_context = design;
}
// lookup the module with the given name in the current design context
static const RTLIL::Module* lookup_module(const std::string &name)
{
return simplify_design_context->module(name);
}
const RTLIL::Module* AstNode::lookup_cell_module()
{
log_assert(type == AST_CELL);
auto reprocess_after = [this] (const std::string &modname) {
if (!attributes.count(ID::reprocess_after))
neater errors, lost in the sauce of source
2025-06-18 18:05:48 +02:00
set_attribute(ID::reprocess_after, AstNode::mkconst_str(location, modname));
verilog: use derived module info to elaborate cell connections - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
2021-10-20 02:46:26 +02:00
};
const AstNode *celltype = nullptr;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : children)
verilog: use derived module info to elaborate cell connections - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
2021-10-20 02:46:26 +02:00
if (child->type == AST_CELLTYPE) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
celltype = child.get();
verilog: use derived module info to elaborate cell connections - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
2021-10-20 02:46:26 +02:00
break;
}
log_assert(celltype != nullptr);
const RTLIL::Module *module = lookup_module(celltype->str);
if (!module)
module = lookup_module("$abstract" + celltype->str);
if (!module) {
if (celltype->str.at(0) != '$')
reprocess_after(celltype->str);
return nullptr;
}
// build a mapping from true param name to param value
size_t para_counter = 0;
dict<RTLIL::IdString, RTLIL::Const> cell_params_map;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : children) {
verilog: use derived module info to elaborate cell connections - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
2021-10-20 02:46:26 +02:00
if (child->type != AST_PARASET)
continue;
if (child->str.empty() && para_counter >= module->avail_parameters.size())
return nullptr; // let hierarchy handle this error
IdString paraname = child->str.empty() ? module->avail_parameters[para_counter++] : child->str;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
const AstNode *value = child->children[0].get();
verilog: use derived module info to elaborate cell connections - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
2021-10-20 02:46:26 +02:00
if (value->type != AST_REALVALUE && value->type != AST_CONSTANT)
return nullptr; // let genrtlil handle this error
cell_params_map[paraname] = value->asParaConst();
}
// put the parameters in order and generate the derived module name
std::vector<std::pair<RTLIL::IdString, RTLIL::Const>> named_parameters;
for (RTLIL::IdString param : module->avail_parameters) {
auto it = cell_params_map.find(param);
if (it != cell_params_map.end())
named_parameters.emplace_back(it->first, it->second);
}
std::string modname = celltype->str;
if (cell_params_map.size()) // not named_parameters to cover hierarchical defparams
modname = derived_module_name(celltype->str, named_parameters);
// try to find the resolved module
module = lookup_module(modname);
if (!module) {
reprocess_after(modname);
return nullptr;
}
return module;
}
// returns whether an expression contains an unbased unsized literal; does not
// check the literal exists in a self-determined context
static bool contains_unbased_unsized(const AstNode *node)
{
if (node->type == AST_CONSTANT)
return node->is_unsized;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : node->children)
if (contains_unbased_unsized(child.get()))
verilog: use derived module info to elaborate cell connections - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
2021-10-20 02:46:26 +02:00
return true;
return false;
}
// adds a wire to the current module with the given name that matches the
// dimensions of the given wire reference
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
void add_wire_for_ref(location loc, const RTLIL::Wire *ref, const std::string &str)
verilog: use derived module info to elaborate cell connections - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
2021-10-20 02:46:26 +02:00
{
frontends/ast: More usage of auto For consistency.
2025-08-08 07:10:16 +02:00
auto left = AstNode::mkconst_int(loc, ref->width - 1 + ref->start_offset, true);
auto right = AstNode::mkconst_int(loc, ref->start_offset, true);
verilog: use derived module info to elaborate cell connections - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
2021-10-20 02:46:26 +02:00
if (ref->upto)
std::swap(left, right);
frontends/ast: More usage of auto For consistency.
2025-08-08 07:10:16 +02:00
auto range = std::make_unique<AstNode>(loc, AST_RANGE, std::move(left), std::move(right));
verilog: use derived module info to elaborate cell connections - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
2021-10-20 02:46:26 +02:00
frontends/ast: More usage of auto For consistency.
2025-08-08 07:10:16 +02:00
auto wire = std::make_unique<AstNode>(loc, AST_WIRE, std::move(range));
verilog: use derived module info to elaborate cell connections - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
2021-10-20 02:46:26 +02:00
wire->is_signed = ref->is_signed;
wire->is_logic = true;
wire->str = str;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_scope[str] = wire.get();
current_ast_mod->children.push_back(std::move(wire));
verilog: use derived module info to elaborate cell connections - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
2021-10-20 02:46:26 +02:00
}
sv: auto add nosync to certain always_comb local vars If a local variable is always assigned before it is used, then adding nosync prevents latches from being needlessly generated.
2022-01-07 06:04:00 +01:00
enum class IdentUsage {
NotReferenced, // target variable is neither read or written in the block
Assigned, // target variable is always assigned before use
SyncRequired, // target variable may be used before it has been assigned
};
// determines whether a local variable a block is always assigned before it is
// used, meaning the nosync attribute can automatically be added to that
// variable
static IdentUsage always_asgn_before_use(const AstNode *node, const std::string &target)
{
// This variable has been referenced before it has necessarily been assigned
// a value in this procedure.
if (node->type == AST_IDENTIFIER && node->str == target)
return IdentUsage::SyncRequired;
// For case statements (which are also used for if/else), we check each
// possible branch. If the variable is assigned in all branches, then it is
// assigned, and a sync isn't required. If it used before assignment in any
// branch, then a sync is required.
if (node->type == AST_CASE) {
bool all_defined = true;
bool any_used = false;
bool has_default = false;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : node->children) {
sv: auto add nosync to certain always_comb local vars If a local variable is always assigned before it is used, then adding nosync prevents latches from being needlessly generated.
2022-01-07 06:04:00 +01:00
if (child->type == AST_COND && child->children.at(0)->type == AST_DEFAULT)
has_default = true;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
IdentUsage nested = always_asgn_before_use(child.get(), target);
sv: auto add nosync to certain always_comb local vars If a local variable is always assigned before it is used, then adding nosync prevents latches from being needlessly generated.
2022-01-07 06:04:00 +01:00
if (nested != IdentUsage::Assigned && child->type == AST_COND)
all_defined = false;
if (nested == IdentUsage::SyncRequired)
any_used = true;
}
if (any_used)
return IdentUsage::SyncRequired;
else if (all_defined && has_default)
return IdentUsage::Assigned;
else
return IdentUsage::NotReferenced;
}
// Check if this is an assignment to the target variable. For simplicity, we
// don't analyze sub-ranges of the variable.
if (node->type == AST_ASSIGN_EQ) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto& ident = node->children.at(0);
sv: auto add nosync to certain always_comb local vars If a local variable is always assigned before it is used, then adding nosync prevents latches from being needlessly generated.
2022-01-07 06:04:00 +01:00
if (ident->type == AST_IDENTIFIER && ident->str == target)
return IdentUsage::Assigned;
}
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : node->children) {
IdentUsage nested = always_asgn_before_use(child.get(), target);
sv: auto add nosync to certain always_comb local vars If a local variable is always assigned before it is used, then adding nosync prevents latches from being needlessly generated.
2022-01-07 06:04:00 +01:00
if (nested != IdentUsage::NotReferenced)
return nested;
}
return IdentUsage::NotReferenced;
}
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
std::unique_ptr<AstNode> AstNode::clone_at_zero()
ast/simplify: Use clone_at_zero() for "at_zero" evaluations The correct way of using the 'at_zero' regime of simplify is to perform the simplification on a cloned AST subtree, otherwise the "at_zero" evaluation seeps into the main tree. Move the effect of the 'at_zero' flag to the cloning itself, so that the simplify flag can be retired. We assume we can rely on id2ast in the new clone method.
2023-06-21 13:45:42 +02:00
{
int width_hint;
bool sign_hint;
AstNode *pointee;
switch (type) {
case AST_IDENTIFIER:
if (id2ast)
pointee = id2ast;
else if (current_scope.count(str))
pointee = current_scope[str];
else
break;
if (pointee->type != AST_WIRE &&
pointee->type != AST_AUTOWIRE &&
pointee->type != AST_MEMORY)
break;
Add new `$check` cell to represent assertions with a message.
2024-01-11 10:39:28 +01:00
YS_FALLTHROUGH
ast/simplify: Use clone_at_zero() for "at_zero" evaluations The correct way of using the 'at_zero' regime of simplify is to perform the simplification on a cloned AST subtree, otherwise the "at_zero" evaluation seeps into the main tree. Move the effect of the 'at_zero' flag to the cloning itself, so that the simplify flag can be retired. We assume we can rely on id2ast in the new clone method.
2023-06-21 13:45:42 +02:00
case AST_MEMRD:
detectSignWidth(width_hint, sign_hint);
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
return mkconst_int(location, 0, sign_hint, width_hint);
ast/simplify: Use clone_at_zero() for "at_zero" evaluations The correct way of using the 'at_zero' regime of simplify is to perform the simplification on a cloned AST subtree, otherwise the "at_zero" evaluation seeps into the main tree. Move the effect of the 'at_zero' flag to the cloning itself, so that the simplify flag can be retired. We assume we can rely on id2ast in the new clone method.
2023-06-21 13:45:42 +02:00
default:
break;
}
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto that = clone();
ast/simplify: Use clone_at_zero() for "at_zero" evaluations The correct way of using the 'at_zero' regime of simplify is to perform the simplification on a cloned AST subtree, otherwise the "at_zero" evaluation seeps into the main tree. Move the effect of the 'at_zero' flag to the cloning itself, so that the simplify flag can be retired. We assume we can rely on id2ast in the new clone method.
2023-06-21 13:45:42 +02:00
for (auto &it : that->children)
it = it->clone_at_zero();
for (auto &it : that->attributes)
it.second = it.second->clone();
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
that->set_in_lvalue_flag(false);
that->set_in_param_flag(false);
that->fixup_hierarchy_flags();
ast/simplify: Use clone_at_zero() for "at_zero" evaluations The correct way of using the 'at_zero' regime of simplify is to perform the simplification on a cloned AST subtree, otherwise the "at_zero" evaluation seeps into the main tree. Move the effect of the 'at_zero' flag to the cloning itself, so that the simplify flag can be retired. We assume we can rely on id2ast in the new clone method.
2023-06-21 13:45:42 +02:00
return that;
}
ast/simplify: Factor out helper to determine range width
2023-04-04 11:34:17 +02:00
static bool try_determine_range_width(AstNode *range, int &result_width)
{
log_assert(range->type == AST_RANGE);
if (range->children.size() == 1) {
result_width = 1;
return true;
}
frontends/ast: More usage of auto For consistency.
2025-08-08 07:10:16 +02:00
auto left_at_zero_ast = range->children[0]->clone_at_zero();
auto right_at_zero_ast = range->children[1]->clone_at_zero();
ast/simplify: Factor out helper to determine range width
2023-04-04 11:34:17 +02:00
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (left_at_zero_ast->simplify(true, 1, -1, false)) {}
while (right_at_zero_ast->simplify(true, 1, -1, false)) {}
ast/simplify: Factor out helper to determine range width
2023-04-04 11:34:17 +02:00
bool ok = false;
if (left_at_zero_ast->type == AST_CONSTANT
&& right_at_zero_ast->type == AST_CONSTANT) {
ok = true;
result_width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1;
}
return ok;
}
sv: auto add nosync to certain always_comb local vars If a local variable is always assigned before it is used, then adding nosync prevents latches from being needlessly generated.
2022-01-07 06:04:00 +01:00
static const std::string auto_nosync_prefix = "\\AutoNosync";
// mark a local variable in an always_comb block for automatic nosync
// consideration
static void mark_auto_nosync(AstNode *block, const AstNode *wire)
{
log_assert(block->type == AST_BLOCK);
log_assert(wire->type == AST_WIRE);
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
block->set_attribute(auto_nosync_prefix + wire->str, AstNode::mkconst_int(block->location, 1, false));
sv: auto add nosync to certain always_comb local vars If a local variable is always assigned before it is used, then adding nosync prevents latches from being needlessly generated.
2022-01-07 06:04:00 +01:00
}
sv: fix always_comb auto nosync for nested and function blocks
2022-02-22 16:57:08 +01:00
// block names can be prefixed with an explicit scope during elaboration
static bool is_autonamed_block(const std::string &str) {
size_t last_dot = str.rfind('.');
// unprefixed names: autonamed if the first char is a dollar sign
if (last_dot == std::string::npos)
return str.at(0) == '$'; // e.g., `$fordecl_block$1`
// prefixed names: autonamed if the final chunk begins with a dollar sign
return str.rfind(".$") == last_dot; // e.g., `\foo.bar.$fordecl_block$1`
}
sv: auto add nosync to certain always_comb local vars If a local variable is always assigned before it is used, then adding nosync prevents latches from being needlessly generated.
2022-01-07 06:04:00 +01:00
// check a procedural block for auto-nosync markings, remove them, and add
// nosync to local variables as necessary
static void check_auto_nosync(AstNode *node)
{
std::vector<RTLIL::IdString> attrs_to_drop;
for (const auto& elem : node->attributes) {
// skip attributes that don't begin with the prefix
if (elem.first.compare(0, auto_nosync_prefix.size(),
auto_nosync_prefix.c_str()))
continue;
// delete and remove the attribute once we're done iterating
attrs_to_drop.push_back(elem.first);
// find the wire based on the attribute
std::string wire_name = elem.first.substr(auto_nosync_prefix.size());
auto it = current_scope.find(wire_name);
if (it == current_scope.end())
continue;
// analyze the usage of the local variable in this block
IdentUsage ident_usage = always_asgn_before_use(node, wire_name);
if (ident_usage != IdentUsage::Assigned)
continue;
// mark the wire with `nosync`
AstNode *wire = it->second;
log_assert(wire->type == AST_WIRE);
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
wire->set_attribute(ID::nosync, AstNode::mkconst_int(wire->location, 1, false));
sv: auto add nosync to certain always_comb local vars If a local variable is always assigned before it is used, then adding nosync prevents latches from being needlessly generated.
2022-01-07 06:04:00 +01:00
}
// remove the attributes we've "consumed"
for (const RTLIL::IdString &str : attrs_to_drop) {
auto it = node->attributes.find(str);
node->attributes.erase(it);
}
// check local variables in any nested blocks
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : node->children)
check_auto_nosync(child.get());
}
Spell check (by Larry Doolittle)
2015-08-14 10:56:05 +02:00
// convert the AST into a simpler AST that has all parameters substituted by their
initial import
2013-01-05 11:13:26 +01:00
// values, unrolled for-loops, expanded generate blocks, etc. when this function
// is done with an AST it can be converted into RTLIL using genRTLIL().
//
// this function also does all name resolving and sets the id2ast member of all
// nodes that link to a different node using names and lexical scoping.
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hint)
initial import
2013-01-05 11:13:26 +01:00
{
Added AstNode::simplify() recursion counter
2015-02-13 12:33:12 +01:00
static int recursion_counter = 0;
Added deep recursion warning to AST simplify
2015-02-20 10:33:20 +01:00
static bool deep_recursion_warning = false;
if (recursion_counter++ == 1000 && deep_recursion_warning) {
Extend simplify() recursion warning
2021-02-25 22:02:55 +01:00
log_warning("Deep recursion in AST simplifier.\nDoes this design contain overly long or deeply nested expressions, or excessive recursion?\n");
Added deep recursion warning to AST simplify
2015-02-20 10:33:20 +01:00
deep_recursion_warning = false;
}
Added AstNode::simplify() recursion counter
2015-02-13 12:33:12 +01:00
verilog: support recursive functions using ternary expressions This adds a mechanism for marking certain portions of elaboration as occurring within unevaluated ternary branches. To enable elaboration of the overall ternary, this also adds width detection for these unelaborated function calls.
2021-02-12 20:25:34 +01:00
static bool unevaluated_tern_branch = false;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
std::unique_ptr<AstNode> newNode = nullptr;
initial import
2013-01-05 11:13:26 +01:00
bool did_something = false;
Added handling of real-valued parameters/localparams
2014-06-14 12:00:47 +02:00
#if 0
log("-------------\n");
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
log("AST simplify[%d] depth %d at %s:%d on %s %p:\n", stage, recursion_counter, location.begin.filename->c_str(), location.begin.line, type2str(type).c_str(), this);
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
log("const_fold=%d, stage=%d, width_hint=%d, sign_hint=%d\n",
int(const_fold), int(stage), int(width_hint), int(sign_hint));
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
// dumpAst(nullptr, "> ");
Added handling of real-valued parameters/localparams
2014-06-14 12:00:47 +02:00
#endif
initial import
2013-01-05 11:13:26 +01:00
if (stage == 0)
{
Synthesis support for SystemVerilog interfaces This time doing the changes mostly in AST before RTLIL generation
2018-10-11 23:33:31 +02:00
log_assert(type == AST_MODULE || type == AST_INTERFACE);
initial import
2013-01-05 11:13:26 +01:00
Added deep recursion warning to AST simplify
2015-02-20 10:33:20 +01:00
deep_recursion_warning = true;
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (simplify(const_fold, 1, width_hint, sign_hint)) { }
initial import
2013-01-05 11:13:26 +01:00
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 18:51:32 +02:00
if (!flag_nomem2reg && !get_bool_attribute(ID::nomem2reg))
initial import
2013-01-05 11:13:26 +01:00
{
dict/pool changes in ast
2014-12-29 03:11:50 +01:00
dict<AstNode*, pool<std::string>> mem2reg_places;
dict<AstNode*, uint32_t> mem2reg_candidates, dummy_proc_flags;
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
uint32_t flags = flag_mem2reg ? AstNode::MEM2REG_FL_ALL : 0;
mem2reg_as_needed_pass1(mem2reg_places, mem2reg_candidates, dummy_proc_flags, flags);
dict/pool changes in ast
2014-12-29 03:11:50 +01:00
pool<AstNode*> mem2reg_set;
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
for (auto &it : mem2reg_candidates)
{
AstNode *mem = it.first;
uint32_t memflags = it.second;
Added "read_verilog -nomeminit" and "nomeminit" attribute
2015-02-14 11:21:12 +01:00
bool this_nomeminit = flag_nomeminit;
Using log_assert() instead of assert()
2014-07-28 11:08:55 +02:00
log_assert((memflags & ~0x00ffff00) == 0);
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 18:51:32 +02:00
if (mem->get_bool_attribute(ID::nomem2reg))
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
continue;
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 18:51:32 +02:00
if (mem->get_bool_attribute(ID::nomeminit) || get_bool_attribute(ID::nomeminit))
Added "read_verilog -nomeminit" and "nomeminit" attribute
2015-02-14 11:21:12 +01:00
this_nomeminit = true;
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
if (memflags & AstNode::MEM2REG_FL_FORCED)
goto silent_activate;
if (memflags & AstNode::MEM2REG_FL_EQ2)
goto verbose_activate;
Fixed async proc detection in mem2reg
2013-11-21 21:26:56 +01:00
if (memflags & AstNode::MEM2REG_FL_SET_ASYNC)
goto verbose_activate;
Added "read_verilog -nomeminit" and "nomeminit" attribute
2015-02-14 11:21:12 +01:00
if ((memflags & AstNode::MEM2REG_FL_SET_INIT) && (memflags & AstNode::MEM2REG_FL_SET_ELSE) && this_nomeminit)
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
goto verbose_activate;
Added AstNode::MEM2REG_FL_CMPLX_LHS
2014-06-17 21:39:25 +02:00
if (memflags & AstNode::MEM2REG_FL_CMPLX_LHS)
goto verbose_activate;
Use mem2reg on memories that only have constant-index write ports Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-01 22:35:09 +01:00
if ((memflags & AstNode::MEM2REG_FL_CONST_LHS) && !(memflags & AstNode::MEM2REG_FL_VAR_LHS))
goto verbose_activate;
Fixed async proc detection in mem2reg
2013-11-21 21:26:56 +01:00
// log("Note: Not replacing memory %s with list of registers (flags=0x%08lx).\n", mem->str.c_str(), long(memflags));
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
continue;
verbose_activate:
if (mem2reg_set.count(mem) == 0) {
Fixed mem2reg warning message
2014-12-27 03:26:30 +01:00
std::string message = stringf("Replacing memory %s with list of registers.", mem->str.c_str());
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
bool first_element = true;
for (auto &place : mem2reg_places[it.first]) {
Fixed mem2reg warning message
2014-12-27 03:26:30 +01:00
message += stringf("%s%s", first_element ? " See " : ", ", place.c_str());
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
first_element = false;
}
Fixed mem2reg warning message
2014-12-27 03:26:30 +01:00
log_warning("%s\n", message.c_str());
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
}
silent_activate:
Fixed async proc detection in mem2reg
2013-11-21 21:26:56 +01:00
// log("Note: Replacing memory %s with list of registers (flags=0x%08lx).\n", mem->str.c_str(), long(memflags));
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
mem2reg_set.insert(mem);
}
initial import
2013-01-05 11:13:26 +01:00
for (auto node : mem2reg_set)
{
int mem_width, mem_size, addr_bits;
node->meminfo(mem_width, mem_size, addr_bits);
Fix mem2reg handling of memories with upto data ports, fixes #888 Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-21 22:19:17 +01:00
int data_range_left = node->children[0]->range_left;
int data_range_right = node->children[0]->range_right;
if (node->children[0]->range_swapped)
std::swap(data_range_left, data_range_right);
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto loc = node->location;
initial import
2013-01-05 11:13:26 +01:00
for (int i = 0; i < mem_size; i++) {
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto reg = std::make_unique<AstNode>(loc, AST_WIRE, std::make_unique<AstNode>(loc, AST_RANGE,
mkconst_int(loc, data_range_left, true), mkconst_int(loc, data_range_right, true)));
initial import
2013-01-05 11:13:26 +01:00
reg->str = stringf("%s[%d]", node->str.c_str(), i);
reg->is_reg = true;
reg->is_signed = node->is_signed;
mem2reg to preserve user attributes and src
2019-08-21 22:36:01 +02:00
for (auto &it : node->attributes)
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 18:51:32 +02:00
if (it.first != ID::mem2reg)
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
reg->set_attribute(it.first, it.second->clone());
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
reg->location.begin.filename = node->location.begin.filename;
Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
2020-02-23 08:19:52 +01:00
reg->location = node->location;
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (reg->simplify(true, 1, -1, false)) { }
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
children.push_back(std::move(reg));
initial import
2013-01-05 11:13:26 +01:00
}
}
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
AstNode* async_block = nullptr;
while (mem2reg_as_needed_pass2(mem2reg_set, this, nullptr, async_block)) { }
Fixed access-after-delete bug in mem2reg code
2016-05-27 17:25:33 +02:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
mem2reg_remove(mem2reg_set);
initial import
2013-01-05 11:13:26 +01:00
}
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (simplify(const_fold, 2, width_hint, sign_hint)) { }
Added AstNode::simplify() recursion counter
2015-02-13 12:33:12 +01:00
recursion_counter--;
initial import
2013-01-05 11:13:26 +01:00
return false;
}
// we do not look inside a task or function
Spell check (by Larry Doolittle)
2015-08-14 10:56:05 +02:00
// (but as soon as a task or function is instantiated we process the generated AST as usual)
Added AstNode::simplify() recursion counter
2015-02-13 12:33:12 +01:00
if (type == AST_FUNCTION || type == AST_TASK) {
recursion_counter--;
initial import
2013-01-05 11:13:26 +01:00
return false;
Added AstNode::simplify() recursion counter
2015-02-13 12:33:12 +01:00
}
initial import
2013-01-05 11:13:26 +01:00
Spell check (by Larry Doolittle)
2015-08-14 10:56:05 +02:00
// deactivate all calls to non-synthesis system tasks
Added support for $stop system task
2016-03-21 16:19:51 +01:00
// note that $display, $finish, and $stop are used for synthesis-time DRC so they're not in this list
if ((type == AST_FCALL || type == AST_TCALL) && (str == "$strobe" || str == "$monitor" || str == "$time" ||
Ignoring more system task and functions
2015-01-15 13:08:19 +01:00
str == "$dumpfile" || str == "$dumpvars" || str == "$dumpon" || str == "$dumpoff" || str == "$dumpall")) {
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
log_file_warning(*location.begin.filename, location.begin.line, "Ignoring call to system %s %s.\n", type == AST_FCALL ? "function" : "task", str.c_str());
initial import
2013-01-05 11:13:26 +01:00
delete_children();
str = std::string();
}
ast: use new format string helpers.
2020-11-29 09:57:07 +01:00
if ((type == AST_TCALL) &&
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
(str == "$display" || str == "$displayb" || str == "$displayh" || str == "$displayo" ||
str == "$write" || str == "$writeb" || str == "$writeh" || str == "$writeo"))
Initial implementation of $display()
2015-09-18 05:34:56 +02:00
{
ast: translate $display/$write tasks in always blocks to new $print cell.
2020-11-29 15:34:17 +01:00
if (!current_always) {
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
log_file_warning(*location.begin.filename, location.begin.line, "System task `%s' outside initial or always block is unsupported.\n", str.c_str());
Optionally suppress output from display system tasks in read_verilog
2024-01-11 10:32:44 +01:00
delete_children();
str = std::string();
ast: translate $display/$write tasks in always blocks to new $print cell.
2020-11-29 15:34:17 +01:00
} else {
Optionally suppress output from display system tasks in read_verilog
2024-01-11 10:32:44 +01:00
// simplify the expressions and convert them to a special cell later in genrtlil
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& node : children)
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (node->simplify(true, stage, -1, false)) {}
Optionally suppress output from display system tasks in read_verilog
2024-01-11 10:32:44 +01:00
if (current_always->type == AST_INITIAL && !flag_nodisplay && stage == 2) {
int default_base = 10;
if (str.back() == 'b')
default_base = 2;
else if (str.back() == 'o')
default_base = 8;
else if (str.back() == 'h')
default_base = 16;
// when $display()/$write() functions are used in an initial block, print them during synthesis
Fmt fmt = processFormat(stage, /*sformat_like=*/false, default_base, /*first_arg_at=*/0, /*may_fail=*/true);
if (str.substr(0, 8) == "$display")
fmt: `FmtPart::{STRING→LITERAL},{CHARACTER→STRING}`. Before this commit, the `STRING` variant inserted a literal string; the `CHARACTER` variant inserted a string. This commit renames them to `LITERAL` and `STRING` respectively.
2024-03-28 07:30:16 +01:00
fmt.append_literal("\n");
Optionally suppress output from display system tasks in read_verilog
2024-01-11 10:32:44 +01:00
log("%s", fmt.render().c_str());
}
ast: translate $display/$write tasks in always blocks to new $print cell.
2020-11-29 15:34:17 +01:00
return false;
}
Initial implementation of $display()
2015-09-18 05:34:56 +02:00
}
initial import
2013-01-05 11:13:26 +01:00
// activate const folding if this is anything that must be evaluated statically (ranges, parameters, attributes, etc.)
partial rebase of PeterCrozier's enum work onto current master I tried to keep only the enum-related changes, and minimize the diff. (The original commit also had a lot of work done to get typedefs working, but yosys has diverged quite a bit since the 2018-03-09 commit, with a new typedef implementation.) I did not include the import related changes either. Original commit: "Initial implementation of enum, typedef, import. Still a WIP." https://github.com/PeterCrozier/yosys/commit/881833aa738e7404987646ea8076284e911fce3f
2018-03-09 13:47:11 +01:00
if (type == AST_WIRE || type == AST_PARAMETER || type == AST_LOCALPARAM || type == AST_ENUM_ITEM || type == AST_DEFPARAM || type == AST_PARASET || type == AST_RANGE || type == AST_PREFIX || type == AST_TYPEDEF)
Be more conservative with new const-function code
2014-02-14 20:45:30 +01:00
const_fold = true;
partial rebase of PeterCrozier's enum work onto current master I tried to keep only the enum-related changes, and minimize the diff. (The original commit also had a lot of work done to get typedefs working, but yosys has diverged quite a bit since the 2018-03-09 commit, with a new typedef implementation.) I did not include the import related changes either. Original commit: "Initial implementation of enum, typedef, import. Still a WIP." https://github.com/PeterCrozier/yosys/commit/881833aa738e7404987646ea8076284e911fce3f
2018-03-09 13:47:11 +01:00
if (type == AST_IDENTIFIER && current_scope.count(str) > 0 && (current_scope[str]->type == AST_PARAMETER || current_scope[str]->type == AST_LOCALPARAM || current_scope[str]->type == AST_ENUM_ITEM))
initial import
2013-01-05 11:13:26 +01:00
const_fold = true;
std::map<std::string, AstNode*> backup_scope;
// create name resolution entries for all objects with names
// also merge multiple declarations for the same wire (e.g. "output foobar; reg foobar;")
Resolve package types in interfaces (#3658) * Resolve package types in interfaces * Added test for resolving of package types in interfaces
2023-02-13 00:25:39 +01:00
if (type == AST_MODULE || type == AST_INTERFACE) {
initial import
2013-01-05 11:13:26 +01:00
current_scope.clear();
verilog: significant block scoping improvements This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
2021-01-27 19:30:22 +01:00
std::set<std::string> existing;
int counter = 0;
label_genblks(existing, counter);
initial import
2013-01-05 11:13:26 +01:00
std::map<std::string, AstNode*> this_wire_scope;
fix whitespace issues
2025-08-06 21:32:36 +02:00
implement package import
2025-08-04 05:31:54 +02:00
// Process package imports after clearing the scope but before processing module declarations
add safety checks and better name matching
2025-08-05 02:57:43 +02:00
for (size_t i = 0; i < children.size(); i++) {
ast: fix import node
2025-08-08 16:15:20 +02:00
AstNode *child = children[i].get();
implement package import
2025-08-04 05:31:54 +02:00
if (child->type == AST_IMPORT) {
// Find the package in the design
AstNode *package_node = nullptr;
fix whitespace issues
2025-08-06 21:32:36 +02:00
add separate module test
2025-08-04 05:48:33 +02:00
// First look in current_ast->children (for packages in same file)
add safety checks and better name matching
2025-08-05 02:57:43 +02:00
if (current_ast != nullptr) {
for (auto &design_child : current_ast->children) {
if (design_child->type == AST_PACKAGE) {
if (design_child->str == child->str) {
ast: fix import node
2025-08-08 16:15:20 +02:00
package_node = design_child.get();
add safety checks and better name matching
2025-08-05 02:57:43 +02:00
break;
}
add separate module test
2025-08-04 05:48:33 +02:00
}
}
}
fix whitespace issues
2025-08-06 21:32:36 +02:00
add separate module test
2025-08-04 05:48:33 +02:00
// If not found, look in design->verilog_packages (for packages from other files)
if (!package_node && simplify_design_context != nullptr) {
for (auto &design_package : simplify_design_context->verilog_packages) {
add safety checks and better name matching
2025-08-05 02:57:43 +02:00
// Handle both with and without leading backslash
std::string package_name = design_package->str;
if (package_name[0] == '\\') {
package_name = package_name.substr(1);
}
if (package_name == child->str || design_package->str == child->str) {
ast: fix import node
2025-08-08 16:15:20 +02:00
package_node = design_package.get();
add separate module test
2025-08-04 05:48:33 +02:00
break;
}
implement package import
2025-08-04 05:31:54 +02:00
}
}
fix whitespace issues
2025-08-06 21:32:36 +02:00
implement package import
2025-08-04 05:31:54 +02:00
if (package_node) {
// Import all names from the package into current scope
ast: fix import node
2025-08-08 16:15:20 +02:00
for (auto& pkg_child : package_node->children) {
fix whitespace issues
2025-08-06 21:32:36 +02:00
if (pkg_child->type == AST_PARAMETER || pkg_child->type == AST_LOCALPARAM ||
pkg_child->type == AST_TYPEDEF || pkg_child->type == AST_FUNCTION ||
implement package import
2025-08-04 05:31:54 +02:00
pkg_child->type == AST_TASK || pkg_child->type == AST_ENUM) {
ast: fix import node
2025-08-08 16:15:20 +02:00
current_scope[pkg_child->str] = pkg_child.get();
implement package import
2025-08-04 05:31:54 +02:00
}
if (pkg_child->type == AST_ENUM) {
ast: fix import node
2025-08-08 16:15:20 +02:00
for (auto& enode : pkg_child->children) {
implement package import
2025-08-04 05:31:54 +02:00
log_assert(enode->type==AST_ENUM_ITEM);
if (current_scope.count(enode->str) == 0)
ast: fix import node
2025-08-08 16:15:20 +02:00
current_scope[enode->str] = enode.get();
implement package import
2025-08-04 05:31:54 +02:00
else
input_error("enum item %s already exists in current scope\n", enode->str.c_str());
}
}
}
add safety checks and better name matching
2025-08-05 02:57:43 +02:00
// Remove the import node since it's been processed
children.erase(children.begin() + i);
i--; // Adjust index since we removed an element
implement package import
2025-08-04 05:31:54 +02:00
} else {
add safety checks and better name matching
2025-08-05 02:57:43 +02:00
// If we can't find the package, just remove the import node to avoid errors later
log_warning("Package `%s' not found for import, removing import statement\n", child->str.c_str());
children.erase(children.begin() + i);
i--; // Adjust index since we removed an element
implement package import
2025-08-04 05:31:54 +02:00
}
}
}
initial import
2013-01-05 11:13:26 +01:00
for (size_t i = 0; i < children.size(); i++) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
AstNode* node = children[i].get();
sv: Switch parser to glr, prep for typedef Signed-off-by: David Shah <dave@ds0.me>
2019-09-19 21:43:13 +02:00
initial import
2013-01-05 11:13:26 +01:00
if (node->type == AST_WIRE) {
Only run derive on blackbox modules when ports have dynamic size Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-02 21:36:46 +01:00
if (node->children.size() == 1 && node->children[0]->type == AST_RANGE) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& c : node->children[0]->children) {
if (!c->is_simple_const_expr())
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
set_attribute(ID::dynports, AstNode::mkconst_int(c->location, 1, true));
Only run derive on blackbox modules when ports have dynamic size Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-02 21:36:46 +01:00
}
}
initial import
2013-01-05 11:13:26 +01:00
if (this_wire_scope.count(node->str) > 0) {
AstNode *first_node = this_wire_scope[node->str];
This PR should be the base for discussion, do not merge it yet! It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements. What it DOES'T do: Detect registers connected to output ports of instances. Where it FAILS: memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals. You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines)
2018-03-09 09:35:33 +01:00
if (first_node->is_input && node->is_reg)
goto wires_are_incompatible;
Tiny fixes to verilog parser
2013-03-23 18:54:31 +01:00
if (!node->is_input && !node->is_output && node->is_reg && node->children.size() == 0)
goto wires_are_compatible;
Fixed handling of "input foo; reg [0:0] foo;"
2015-01-15 12:53:12 +01:00
if (first_node->children.size() == 0 && node->children.size() == 1 && node->children[0]->type == AST_RANGE) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
AstNode* r = node->children[0].get();
Fixed handling of "input foo; reg [0:0] foo;"
2015-01-15 12:53:12 +01:00
if (r->range_valid && r->range_left == 0 && r->range_right == 0) {
node->children.pop_back();
}
}
initial import
2013-01-05 11:13:26 +01:00
if (first_node->children.size() != node->children.size())
goto wires_are_incompatible;
for (size_t j = 0; j < node->children.size(); j++) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto &n1 = first_node->children[j], &n2 = node->children[j];
initial import
2013-01-05 11:13:26 +01:00
if (n1->type == AST_RANGE && n2->type == AST_RANGE && n1->range_valid && n2->range_valid) {
if (n1->range_left != n2->range_left)
goto wires_are_incompatible;
if (n1->range_right != n2->range_right)
goto wires_are_incompatible;
} else if (*n1 != *n2)
goto wires_are_incompatible;
}
if (first_node->range_left != node->range_left)
goto wires_are_incompatible;
if (first_node->range_right != node->range_right)
goto wires_are_incompatible;
if (first_node->port_id == 0 && (node->is_input || node->is_output))
goto wires_are_incompatible;
Tiny fixes to verilog parser
2013-03-23 18:54:31 +01:00
wires_are_compatible:
initial import
2013-01-05 11:13:26 +01:00
if (node->is_input)
first_node->is_input = true;
if (node->is_output)
first_node->is_output = true;
if (node->is_reg)
first_node->is_reg = true;
This PR should be the base for discussion, do not merge it yet! It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements. What it DOES'T do: Detect registers connected to output ports of instances. Where it FAILS: memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals. You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines)
2018-03-09 09:35:33 +01:00
if (node->is_logic)
first_node->is_logic = true;
initial import
2013-01-05 11:13:26 +01:00
if (node->is_signed)
first_node->is_signed = true;
for (auto &it : node->attributes) {
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
first_node->set_attribute(it.first, it.second->clone());
initial import
2013-01-05 11:13:26 +01:00
}
children.erase(children.begin()+(i--));
did_something = true;
continue;
Fixed merging of compatible wire decls in AST frontend
2014-03-05 19:55:58 +01:00
wires_are_incompatible:
if (stage > 1)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Incompatible re-declaration of wire %s.\n", node->str.c_str());
Fixed merging of compatible wire decls in AST frontend
2014-03-05 19:55:58 +01:00
continue;
initial import
2013-01-05 11:13:26 +01:00
}
this_wire_scope[node->str] = node;
}
partial rebase of PeterCrozier's enum work onto current master I tried to keep only the enum-related changes, and minimize the diff. (The original commit also had a lot of work done to get typedefs working, but yosys has diverged quite a bit since the 2018-03-09 commit, with a new typedef implementation.) I did not include the import related changes either. Original commit: "Initial implementation of enum, typedef, import. Still a WIP." https://github.com/PeterCrozier/yosys/commit/881833aa738e7404987646ea8076284e911fce3f
2018-03-09 13:47:11 +01:00
// these nodes appear at the top level in a module and can define names
initial import
2013-01-05 11:13:26 +01:00
if (node->type == AST_PARAMETER || node->type == AST_LOCALPARAM || node->type == AST_WIRE || node->type == AST_AUTOWIRE || node->type == AST_GENVAR ||
sv: Switch parser to glr, prep for typedef Signed-off-by: David Shah <dave@ds0.me>
2019-09-19 21:43:13 +02:00
node->type == AST_MEMORY || node->type == AST_FUNCTION || node->type == AST_TASK || node->type == AST_DPI_FUNCTION || node->type == AST_CELL ||
node->type == AST_TYPEDEF) {
initial import
2013-01-05 11:13:26 +01:00
backup_scope[node->str] = current_scope[node->str];
current_scope[node->str] = node;
}
partial rebase of PeterCrozier's enum work onto current master I tried to keep only the enum-related changes, and minimize the diff. (The original commit also had a lot of work done to get typedefs working, but yosys has diverged quite a bit since the 2018-03-09 commit, with a new typedef implementation.) I did not include the import related changes either. Original commit: "Initial implementation of enum, typedef, import. Still a WIP." https://github.com/PeterCrozier/yosys/commit/881833aa738e7404987646ea8076284e911fce3f
2018-03-09 13:47:11 +01:00
if (node->type == AST_ENUM) {
add attributes for enumerated values in ilang - information also useful for strongly-typed enums (not implemented) - resolves enum values in ilang part of #1594 - still need to output enums to VCD (or better yet FST) files
2020-02-03 07:12:24 +01:00
current_scope[node->str] = node;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& enode : node->children) {
partial rebase of PeterCrozier's enum work onto current master I tried to keep only the enum-related changes, and minimize the diff. (The original commit also had a lot of work done to get typedefs working, but yosys has diverged quite a bit since the 2018-03-09 commit, with a new typedef implementation.) I did not include the import related changes either. Original commit: "Initial implementation of enum, typedef, import. Still a WIP." https://github.com/PeterCrozier/yosys/commit/881833aa738e7404987646ea8076284e911fce3f
2018-03-09 13:47:11 +01:00
log_assert(enode->type==AST_ENUM_ITEM);
duplicated enum item names should result in an error
2020-04-07 08:30:11 +02:00
if (current_scope.count(enode->str) == 0)
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_scope[enode->str] = enode.get();
duplicated enum item names should result in an error
2020-04-07 08:30:11 +02:00
else
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("enum item %s already exists\n", enode->str.c_str());
partial rebase of PeterCrozier's enum work onto current master I tried to keep only the enum-related changes, and minimize the diff. (The original commit also had a lot of work done to get typedefs working, but yosys has diverged quite a bit since the 2018-03-09 commit, with a new typedef implementation.) I did not include the import related changes either. Original commit: "Initial implementation of enum, typedef, import. Still a WIP." https://github.com/PeterCrozier/yosys/commit/881833aa738e7404987646ea8076284e911fce3f
2018-03-09 13:47:11 +01:00
}
}
initial import
2013-01-05 11:13:26 +01:00
}
Early wire/reg/parameter width calculation in ast/simplify
2013-11-24 19:40:23 +01:00
for (size_t i = 0; i < children.size(); i++) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto& node = children[i];
sv: Switch parser to glr, prep for typedef Signed-off-by: David Shah <dave@ds0.me>
2019-09-19 21:43:13 +02:00
if (node->type == AST_PARAMETER || node->type == AST_LOCALPARAM || node->type == AST_WIRE || node->type == AST_AUTOWIRE || node->type == AST_MEMORY || node->type == AST_TYPEDEF)
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (node->simplify(true, 1, -1, false))
Bugfix in recursive AST simplification
2014-03-05 19:45:33 +01:00
did_something = true;
allow enums to be declared at toplevel scope
2020-01-16 21:23:03 +01:00
if (node->type == AST_ENUM) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& enode : node->children){
allow enums to be declared at toplevel scope
2020-01-16 21:23:03 +01:00
log_assert(enode->type==AST_ENUM_ITEM);
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (node->simplify(true, 1, -1, false))
allow enums to be declared at toplevel scope
2020-01-16 21:23:03 +01:00
did_something = true;
}
}
Early wire/reg/parameter width calculation in ast/simplify
2013-11-24 19:40:23 +01:00
}
sv: auto add nosync to certain always_comb local vars If a local variable is always assigned before it is used, then adding nosync prevents latches from being needlessly generated.
2022-01-07 06:04:00 +01:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : children)
sv: auto add nosync to certain always_comb local vars If a local variable is always assigned before it is used, then adding nosync prevents latches from being needlessly generated.
2022-01-07 06:04:00 +01:00
if (child->type == AST_ALWAYS &&
child->attributes.count(ID::always_comb))
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
check_auto_nosync(child.get());
initial import
2013-01-05 11:13:26 +01:00
}
support using previously declared types/localparams/params in package (parameters in systemverilog packages can't actually be overridden, so allowing parameters in addition to localparams doesn't actually add any new functionality, but it's useful to be able to use the parameter keyword also)
2020-04-07 06:37:44 +02:00
// create name resolution entries for all objects with names
if (type == AST_PACKAGE) {
//add names to package scope
for (size_t i = 0; i < children.size(); i++) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto& node = children[i];
support using previously declared types/localparams/params in package (parameters in systemverilog packages can't actually be overridden, so allowing parameters in addition to localparams doesn't actually add any new functionality, but it's useful to be able to use the parameter keyword also)
2020-04-07 06:37:44 +02:00
// these nodes appear at the top level in a package and can define names
sv: support tasks and functions within packages
2021-05-27 22:47:02 +02:00
if (node->type == AST_PARAMETER || node->type == AST_LOCALPARAM || node->type == AST_TYPEDEF || node->type == AST_FUNCTION || node->type == AST_TASK) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_scope[node->str] = node.get();
support using previously declared types/localparams/params in package (parameters in systemverilog packages can't actually be overridden, so allowing parameters in addition to localparams doesn't actually add any new functionality, but it's useful to be able to use the parameter keyword also)
2020-04-07 06:37:44 +02:00
}
if (node->type == AST_ENUM) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_scope[node->str] = node.get();
for (auto& enode : node->children) {
support using previously declared types/localparams/params in package (parameters in systemverilog packages can't actually be overridden, so allowing parameters in addition to localparams doesn't actually add any new functionality, but it's useful to be able to use the parameter keyword also)
2020-04-07 06:37:44 +02:00
log_assert(enode->type==AST_ENUM_ITEM);
if (current_scope.count(enode->str) == 0)
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_scope[enode->str] = enode.get();
support using previously declared types/localparams/params in package (parameters in systemverilog packages can't actually be overridden, so allowing parameters in addition to localparams doesn't actually add any new functionality, but it's useful to be able to use the parameter keyword also)
2020-04-07 06:37:44 +02:00
else
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("enum item %s already exists in package\n", enode->str.c_str());
support using previously declared types/localparams/params in package (parameters in systemverilog packages can't actually be overridden, so allowing parameters in addition to localparams doesn't actually add any new functionality, but it's useful to be able to use the parameter keyword also)
2020-04-07 06:37:44 +02:00
}
}
}
}
initial import
2013-01-05 11:13:26 +01:00
auto backup_current_block = current_block;
auto backup_current_block_child = current_block_child;
auto backup_current_top_block = current_top_block;
Creating $meminit cells in verilog front-end
2015-02-14 10:49:30 +01:00
auto backup_current_always = current_always;
Avoid creation of bogus initial blocks for assert/assume in always @*
2016-09-06 17:34:42 +02:00
auto backup_current_always_clocked = current_always_clocked;
Creating $meminit cells in verilog front-end
2015-02-14 10:49:30 +01:00
if (type == AST_ALWAYS || type == AST_INITIAL)
Avoid creation of bogus initial blocks for assert/assume in always @*
2016-09-06 17:34:42 +02:00
{
Fix error handling for nested always/initial
2017-12-02 18:52:05 +01:00
if (current_always != nullptr)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Invalid nesting of always blocks and/or initializations.\n");
Fix error handling for nested always/initial
2017-12-02 18:52:05 +01:00
Creating $meminit cells in verilog front-end
2015-02-14 10:49:30 +01:00
current_always = this;
Avoid creation of bogus initial blocks for assert/assume in always @*
2016-09-06 17:34:42 +02:00
current_always_clocked = false;
if (type == AST_ALWAYS)
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : children) {
Avoid creation of bogus initial blocks for assert/assume in always @*
2016-09-06 17:34:42 +02:00
if (child->type == AST_POSEDGE || child->type == AST_NEGEDGE)
current_always_clocked = true;
Allow $past, $stable, $rose, $fell in $global_clock blocks
2017-10-10 11:59:32 +02:00
if (child->type == AST_EDGE && GetSize(child->children) == 1 &&
child->children[0]->type == AST_IDENTIFIER && child->children[0]->str == "\\$global_clock")
current_always_clocked = true;
}
Avoid creation of bogus initial blocks for assert/assume in always @*
2016-09-06 17:34:42 +02:00
}
initial import
2013-01-05 11:13:26 +01:00
verilog: use derived module info to elaborate cell connections - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
2021-10-20 02:46:26 +02:00
if (type == AST_CELL) {
bool lookup_suggested = false;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : children) {
verilog: use derived module info to elaborate cell connections - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
2021-10-20 02:46:26 +02:00
// simplify any parameters to constants
if (child->type == AST_PARASET)
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (child->simplify(true, 1, -1, false)) { }
verilog: use derived module info to elaborate cell connections - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
2021-10-20 02:46:26 +02:00
// look for patterns which _may_ indicate ambiguity requiring
// resolution of the underlying module
if (child->type == AST_ARGUMENT) {
if (child->children.size() != 1)
continue;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
const auto& value = child->children[0];
verilog: use derived module info to elaborate cell connections - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
2021-10-20 02:46:26 +02:00
if (value->type == AST_IDENTIFIER) {
const AstNode *elem = value->id2ast;
if (elem == nullptr) {
if (current_scope.count(value->str))
elem = current_scope.at(value->str);
else
continue;
}
if (elem->type == AST_MEMORY)
// need to determine is the is a read or wire
lookup_suggested = true;
else if (elem->type == AST_WIRE && elem->is_signed && !value->children.empty())
// this may be a fully sliced signed wire which needs
// to be indirected to produce an unsigned connection
lookup_suggested = true;
}
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
else if (contains_unbased_unsized(value.get()))
verilog: use derived module info to elaborate cell connections - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
2021-10-20 02:46:26 +02:00
// unbased unsized literals extend to width of the context
lookup_suggested = true;
}
}
const RTLIL::Module *module = nullptr;
if (lookup_suggested)
module = lookup_cell_module();
if (module) {
size_t port_counter = 0;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : children) {
verilog: use derived module info to elaborate cell connections - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
2021-10-20 02:46:26 +02:00
if (child->type != AST_ARGUMENT)
continue;
// determine the full name of port this argument is connected to
RTLIL::IdString port_name;
if (child->str.size())
port_name = child->str;
else {
if (port_counter >= module->ports.size())
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Cell instance has more ports than the module!\n");
verilog: use derived module info to elaborate cell connections - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
2021-10-20 02:46:26 +02:00
port_name = module->ports[port_counter++];
}
// find the port's wire in the underlying module
const RTLIL::Wire *ref = module->wire(port_name);
if (ref == nullptr)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Cell instance refers to port %s which does not exist in module %s!.\n",
verilog: use derived module info to elaborate cell connections - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
2021-10-20 02:46:26 +02:00
log_id(port_name), log_id(module->name));
// select the argument, if present
log_assert(child->children.size() <= 1);
if (child->children.empty())
continue;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
{
auto arg_check = child->children[0].get();
verilog: use derived module info to elaborate cell connections - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
2021-10-20 02:46:26 +02:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
// plain identifiers never need indirection; this also prevents
// adding infinite levels of indirection
if (arg_check->type == AST_IDENTIFIER && arg_check->children.empty())
continue;
verilog: use derived module info to elaborate cell connections - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
2021-10-20 02:46:26 +02:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
// only add indirection for standard inputs or outputs
if (ref->port_input == ref->port_output)
continue;
}
auto arg = std::move(child->children[0]);
verilog: use derived module info to elaborate cell connections - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
2021-10-20 02:46:26 +02:00
did_something = true;
// create the indirection wire
std::stringstream sstr;
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
sstr << "$indirect$" << ref->name.c_str() << "$" << RTLIL::encode_filename(*location.begin.filename) << ":" << location.begin.line << "$" << (autoidx++);
verilog: use derived module info to elaborate cell connections - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
2021-10-20 02:46:26 +02:00
std::string tmp_str = sstr.str();
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
add_wire_for_ref(location, ref, tmp_str);
verilog: use derived module info to elaborate cell connections - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
2021-10-20 02:46:26 +02:00
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto asgn_owned = std::make_unique<AstNode>(child->location, AST_ASSIGN);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto* asgn = asgn_owned.get();
current_ast_mod->children.push_back(std::move(asgn_owned));
verilog: use derived module info to elaborate cell connections - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
2021-10-20 02:46:26 +02:00
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto ident = std::make_unique<AstNode>(child->location, AST_IDENTIFIER);
verilog: use derived module info to elaborate cell connections - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
2021-10-20 02:46:26 +02:00
ident->str = tmp_str;
child->children[0] = ident->clone();
if (ref->port_input && !ref->port_output) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
asgn->children.push_back(std::move(ident));
asgn->children.push_back(std::move(arg));
verilog: use derived module info to elaborate cell connections - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
2021-10-20 02:46:26 +02:00
} else {
log_assert(!ref->port_input && ref->port_output);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
asgn->children.push_back(std::move(arg));
asgn->children.push_back(std::move(ident));
verilog: use derived module info to elaborate cell connections - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
2021-10-20 02:46:26 +02:00
}
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
asgn->fixup_hierarchy_flags();
verilog: use derived module info to elaborate cell connections - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
2021-10-20 02:46:26 +02:00
}
sv: fix some edge cases for unbased unsized literals - Fix explicit size cast of unbased unsized literals - Fix unbased unsized literal bound directly to port - Output `is_unsized` flag in `dumpAst`
2021-03-03 20:36:19 +01:00
}
}
further improved early width and sign detection in ast simplifier
2013-11-04 06:04:42 +01:00
int backup_width_hint = width_hint;
bool backup_sign_hint = sign_hint;
bool detect_width_simple = false;
bool child_0_is_self_determined = false;
bool child_1_is_self_determined = false;
Fixed handling of mixed real/int ternary expressions
2014-06-25 10:05:36 +02:00
bool child_2_is_self_determined = false;
further improved early width and sign detection in ast simplifier
2013-11-04 06:04:42 +01:00
bool children_are_self_determined = false;
bool reset_width_after_children = false;
switch (type)
{
case AST_ASSIGN_EQ:
case AST_ASSIGN_LE:
case AST_ASSIGN:
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (!children[0]->basic_prep && children[0]->simplify(false, stage, -1, false) == true)
Bugfix in recursive AST simplification
2014-03-05 19:45:33 +01:00
did_something = true;
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (!children[1]->basic_prep && children[1]->simplify(false, stage, -1, false) == true)
Bugfix in recursive AST simplification
2014-03-05 19:45:33 +01:00
did_something = true;
Another fix for early width and sign detection in ast simplifier
2013-11-04 21:29:36 +01:00
children[0]->detectSignWidth(backup_width_hint, backup_sign_hint);
children[1]->detectSignWidth(width_hint, sign_hint);
Import more std:: stuff into Yosys namespace
2015-10-25 19:30:49 +01:00
width_hint = max(width_hint, backup_width_hint);
further improved early width and sign detection in ast simplifier
2013-11-04 06:04:42 +01:00
child_0_is_self_determined = true;
Modified errors into warnings No longer false warnings for memories and assertions
2018-06-05 16:44:24 +02:00
// test only once, before optimizations and memory mappings but after assignment LHS was mapped to an identifier
if (children[0]->id2ast && !children[0]->was_checked) {
if ((type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ) && children[0]->id2ast->is_logic)
children[0]->id2ast->is_reg = true; // if logic type is used in a block asignment
if ((type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ) && !children[0]->id2ast->is_reg)
frontend: Make helper functions for printing locations.
2021-02-23 19:22:53 +01:00
log_warning("wire '%s' is assigned in a block at %s.\n", children[0]->str.c_str(), loc_string().c_str());
Do not generate "reg assigned in a continuous assignment" warnings for "rand reg" Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-01 15:25:24 +01:00
if (type == AST_ASSIGN && children[0]->id2ast->is_reg) {
bool is_rand_reg = false;
if (children[1]->type == AST_FCALL) {
if (children[1]->str == "\\$anyconst")
is_rand_reg = true;
if (children[1]->str == "\\$anyseq")
is_rand_reg = true;
if (children[1]->str == "\\$allconst")
is_rand_reg = true;
if (children[1]->str == "\\$allseq")
is_rand_reg = true;
}
if (!is_rand_reg)
frontend: Make helper functions for printing locations.
2021-02-23 19:22:53 +01:00
log_warning("reg '%s' is assigned in a continuous assignment at %s.\n", children[0]->str.c_str(), loc_string().c_str());
Do not generate "reg assigned in a continuous assignment" warnings for "rand reg" Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-01 15:25:24 +01:00
}
Modified errors into warnings No longer false warnings for memories and assertions
2018-06-05 16:44:24 +02:00
children[0]->was_checked = true;
}
further improved early width and sign detection in ast simplifier
2013-11-04 06:04:42 +01:00
break;
Implement SV structs.
2020-05-08 15:40:49 +02:00
case AST_STRUCT:
Generalise structs and add support for packed unions.
2020-05-12 15:25:33 +02:00
case AST_UNION:
Implement SV structs.
2020-05-08 15:40:49 +02:00
if (!basic_prep) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& node : children) {
Implement SV structs.
2020-05-08 15:40:49 +02:00
// resolve any ranges
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (!node->basic_prep && node->simplify(true, stage, -1, false)) {
Implement SV structs.
2020-05-08 15:40:49 +02:00
did_something = true;
}
}
Generalise structs and add support for packed unions.
2020-05-12 15:25:33 +02:00
// determine member offsets and widths
size_packed_struct(this, 0);
// instance rather than just a type in a typedef or outer struct?
if (!str.empty() && str[0] == '\\') {
// instance so add a wire for the packed structure
Handling of attributes for struct / union variables (* nowrshmsk *) on a struct / union variable now affects dynamic bit slice assignments to members of the struct / union. (* nowrshmsk *) can in some cases yield significant resource savings; the combination of pipeline shifting and indexed writes is an example of this. Constructs similar to the one below can benefit from (* nowrshmsk *), and in addition it is no longer necessary to split out the shift assignments on separate lines in order to avoid the error message "ERROR: incompatible mix of lookahead and non-lookahead IDs in LHS expression." always_ff @(posedge clk) begin if (rotate) begin { v5, v4, v3, v2, v1, v0 } <= { v4, v3, v2, v1, v0, v5 }; if (res) begin v0.bytes <= '0; end else if (w) begin v0.bytes[addr] <= data; end end end
2023-03-02 19:02:30 +01:00
auto wnode = make_packed_struct(this, str, attributes);
Generalise structs and add support for packed unions.
2020-05-12 15:25:33 +02:00
log_assert(current_ast_mod);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_ast_mod->children.push_back(std::move(wnode));
Implement SV structs.
2020-05-08 15:40:49 +02:00
}
Generalise structs and add support for packed unions.
2020-05-12 15:25:33 +02:00
basic_prep = true;
read_verilog: Mark struct as custom type Being a custom type means that it will be resolved *before* (e.g.) a wire can use it as a type.
2025-05-26 02:19:33 +02:00
is_custom_type = false;
Implement SV structs.
2020-05-08 15:40:49 +02:00
}
break;
case AST_STRUCT_ITEM:
Corrected handling of nested typedefs of struct/union This also corrects shadowing of constants in struct/union types.
2023-01-29 20:22:00 +01:00
if (is_custom_type) {
Resolve struct member multiple dimensions defined in stages with typedef
2024-01-05 19:29:06 +01:00
log_assert(children.size() >= 1);
Corrected handling of nested typedefs of struct/union This also corrects shadowing of constants in struct/union types.
2023-01-29 20:22:00 +01:00
log_assert(children[0]->type == AST_WIRETYPE);
Resolve struct member multiple dimensions defined in stages with typedef
2024-01-05 19:29:06 +01:00
// Pretend it's just a wire in order to resolve the type.
type = AST_WIRE;
while (is_custom_type && simplify(const_fold, stage, width_hint, sign_hint)) {};
if (type == AST_WIRE)
Corrected handling of nested typedefs of struct/union This also corrects shadowing of constants in struct/union types.
2023-01-29 20:22:00 +01:00
type = AST_STRUCT_ITEM;
did_something = true;
}
log_assert(!is_custom_type);
Implement SV structs.
2020-05-08 15:40:49 +02:00
break;
partial rebase of PeterCrozier's enum work onto current master I tried to keep only the enum-related changes, and minimize the diff. (The original commit also had a lot of work done to get typedefs working, but yosys has diverged quite a bit since the 2018-03-09 commit, with a new typedef implementation.) I did not include the import related changes either. Original commit: "Initial implementation of enum, typedef, import. Still a WIP." https://github.com/PeterCrozier/yosys/commit/881833aa738e7404987646ea8076284e911fce3f
2018-03-09 13:47:11 +01:00
case AST_ENUM:
separate out enum_item/param implementation when they should be different
2020-02-03 07:08:16 +01:00
//log("\nENUM %s: %d child %d\n", str.c_str(), basic_prep, children[0]->basic_prep);
partial rebase of PeterCrozier's enum work onto current master I tried to keep only the enum-related changes, and minimize the diff. (The original commit also had a lot of work done to get typedefs working, but yosys has diverged quite a bit since the 2018-03-09 commit, with a new typedef implementation.) I did not include the import related changes either. Original commit: "Initial implementation of enum, typedef, import. Still a WIP." https://github.com/PeterCrozier/yosys/commit/881833aa738e7404987646ea8076284e911fce3f
2018-03-09 13:47:11 +01:00
if (!basic_prep) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& item_node : children) {
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (!item_node->basic_prep && item_node->simplify(false, stage, -1, false))
partial rebase of PeterCrozier's enum work onto current master I tried to keep only the enum-related changes, and minimize the diff. (The original commit also had a lot of work done to get typedefs working, but yosys has diverged quite a bit since the 2018-03-09 commit, with a new typedef implementation.) I did not include the import related changes either. Original commit: "Initial implementation of enum, typedef, import. Still a WIP." https://github.com/PeterCrozier/yosys/commit/881833aa738e7404987646ea8076284e911fce3f
2018-03-09 13:47:11 +01:00
did_something = true;
}
// allocate values (called more than once)
allocateDefaultEnumValues();
}
break;
Various fixes for correct parameter support
2013-11-07 09:58:15 +01:00
case AST_PARAMETER:
case AST_LOCALPARAM:
Fix access to whole sub-structs (#3086) * Add support for accessing whole struct * Update tests Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2022-02-14 14:34:20 +01:00
// if parameter is implicit type which is the typename of a struct or union,
// save information about struct in wiretype attribute
if (children[0]->type == AST_IDENTIFIER && current_scope.count(children[0]->str) > 0) {
auto item_node = current_scope[children[0]->str];
if (item_node->type == AST_STRUCT || item_node->type == AST_UNION) {
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
set_attribute(ID::wiretype, item_node->clone());
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
size_packed_struct(attributes[ID::wiretype].get(), 0);
add_members_to_scope(attributes[ID::wiretype].get(), str);
Fix access to whole sub-structs (#3086) * Add support for accessing whole struct * Update tests Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2022-02-14 14:34:20 +01:00
}
}
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (!children[0]->basic_prep && children[0]->simplify(false, stage, -1, false) == true)
Bugfix in recursive AST simplification
2014-03-05 19:45:33 +01:00
did_something = true;
Various fixes for correct parameter support
2013-11-07 09:58:15 +01:00
children[0]->detectSignWidth(width_hint, sign_hint);
Added handling of real-valued parameters/localparams
2014-06-14 12:00:47 +02:00
if (children.size() > 1 && children[1]->type == AST_RANGE) {
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (!children[1]->basic_prep && children[1]->simplify(false, stage, -1, false) == true)
Bugfix in recursive AST simplification
2014-03-05 19:45:33 +01:00
did_something = true;
Various fixes for correct parameter support
2013-11-07 09:58:15 +01:00
if (!children[1]->range_valid)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Non-constant width range on parameter decl.\n");
Import more std:: stuff into Yosys namespace
2015-10-25 19:30:49 +01:00
width_hint = max(width_hint, children[1]->range_left - children[1]->range_right + 1);
Various fixes for correct parameter support
2013-11-07 09:58:15 +01:00
}
break;
separate out enum_item/param implementation when they should be different
2020-02-03 07:08:16 +01:00
case AST_ENUM_ITEM:
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (!children[0]->basic_prep && children[0]->simplify(false, stage, -1, false))
separate out enum_item/param implementation when they should be different
2020-02-03 07:08:16 +01:00
did_something = true;
children[0]->detectSignWidth(width_hint, sign_hint);
if (children.size() > 1 && children[1]->type == AST_RANGE) {
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (!children[1]->basic_prep && children[1]->simplify(false, stage, -1, false))
separate out enum_item/param implementation when they should be different
2020-02-03 07:08:16 +01:00
did_something = true;
if (!children[1]->range_valid)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Non-constant width range on enum item decl.\n");
separate out enum_item/param implementation when they should be different
2020-02-03 07:08:16 +01:00
width_hint = max(width_hint, children[1]->range_left - children[1]->range_right + 1);
}
break;
Various fixes for correct parameter support
2013-11-07 09:58:15 +01:00
Added cast to type support (#4284)
2024-09-29 23:03:01 +02:00
case AST_CAST_SIZE: {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
if (children[0]->type == AST_WIRE) {
int width = 1;
std::unique_ptr<AstNode> node;
frontends/ast: More usage of auto For consistency.
2025-08-08 07:10:16 +02:00
auto* child = children[0].get();
Added cast to type support (#4284)
2024-09-29 23:03:01 +02:00
if (child->children.size() == 0) {
// Base type (e.g., int)
width = child->range_left - child->range_right +1;
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
node = mkconst_int(child->location, width, child->is_signed);
Added cast to type support (#4284)
2024-09-29 23:03:01 +02:00
} else {
// User defined type
log_assert(child->children[0]->type == AST_WIRETYPE);
const std::string &type_name = child->children[0]->str;
if (!current_scope.count(type_name))
input_error("Unknown identifier `%s' used as type name\n", type_name.c_str());
AstNode *resolved_type_node = current_scope.at(type_name);
if (resolved_type_node->type != AST_TYPEDEF)
input_error("`%s' does not name a type\n", type_name.c_str());
log_assert(resolved_type_node->children.size() == 1);
frontends/ast: More usage of auto For consistency.
2025-08-08 07:10:16 +02:00
auto* template_node = resolved_type_node->children[0].get();
Added cast to type support (#4284)
2024-09-29 23:03:01 +02:00
// Ensure typedef itself is fully simplified
while (template_node->simplify(const_fold, stage, width_hint, sign_hint)) {};
switch (template_node->type)
{
case AST_WIRE: {
if (template_node->children.size() > 0 && template_node->children[0]->type == AST_RANGE)
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
width = range_width(this, template_node->children[0].get());
Added cast to type support (#4284)
2024-09-29 23:03:01 +02:00
child->delete_children();
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
node = mkconst_int(child->location, width, true);
Added cast to type support (#4284)
2024-09-29 23:03:01 +02:00
break;
}
case AST_STRUCT:
case AST_UNION: {
child->delete_children();
width = size_packed_struct(template_node, 0);
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
node = mkconst_int(child->location, width, false);
Added cast to type support (#4284)
2024-09-29 23:03:01 +02:00
break;
}
default:
log_error("Don't know how to translate static cast of type %s\n", type2str(template_node->type).c_str());
}
}
children.erase(children.begin());
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
children.insert(children.begin(), std::move(node));
Added cast to type support (#4284)
2024-09-29 23:03:01 +02:00
}
detect_width_simple = true;
children_are_self_determined = true;
break;
}
Added constant size expression support of sized constants
2014-02-01 13:50:23 +01:00
case AST_TO_BITS:
further improved early width and sign detection in ast simplifier
2013-11-04 06:04:42 +01:00
case AST_TO_SIGNED:
case AST_TO_UNSIGNED:
Add AST_SELFSZ and improve handling of bit slices Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-29 14:28:04 +02:00
case AST_SELFSZ:
further improved early width and sign detection in ast simplifier
2013-11-04 06:04:42 +01:00
case AST_CONCAT:
case AST_REPLICATE:
case AST_REDUCE_AND:
case AST_REDUCE_OR:
case AST_REDUCE_XOR:
case AST_REDUCE_XNOR:
case AST_REDUCE_BOOL:
detect_width_simple = true;
children_are_self_determined = true;
break;
case AST_NEG:
case AST_BIT_NOT:
case AST_POS:
case AST_BIT_AND:
case AST_BIT_OR:
case AST_BIT_XOR:
case AST_BIT_XNOR:
case AST_ADD:
case AST_SUB:
case AST_MUL:
case AST_DIV:
case AST_MOD:
detect_width_simple = true;
break;
case AST_SHIFT_LEFT:
case AST_SHIFT_RIGHT:
case AST_SHIFT_SLEFT:
case AST_SHIFT_SRIGHT:
case AST_POW:
detect_width_simple = true;
child_1_is_self_determined = true;
break;
case AST_LT:
case AST_LE:
case AST_EQ:
case AST_NE:
Added proper === and !== support in constant expressions
2013-12-27 13:50:08 +01:00
case AST_EQX:
case AST_NEX:
further improved early width and sign detection in ast simplifier
2013-11-04 06:04:42 +01:00
case AST_GE:
case AST_GT:
width_hint = -1;
sign_hint = true;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : children) {
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (!child->basic_prep && child->simplify(false, stage, -1, false) == true)
Bugfix in recursive AST simplification
2014-03-05 19:45:33 +01:00
did_something = true;
further improved early width and sign detection in ast simplifier
2013-11-04 06:04:42 +01:00
child->detectSignWidthWorker(width_hint, sign_hint);
}
reset_width_after_children = true;
break;
case AST_LOGIC_AND:
case AST_LOGIC_OR:
case AST_LOGIC_NOT:
detect_width_simple = true;
children_are_self_determined = true;
break;
case AST_TERNARY:
child_0_is_self_determined = true;
break;
Fixed trailing whitespaces
2015-07-02 11:14:30 +02:00
further improved early width and sign detection in ast simplifier
2013-11-04 06:04:42 +01:00
case AST_MEMRD:
detect_width_simple = true;
children_are_self_determined = true;
break;
Added $past, $stable, $rose, $fell SVA functions
2016-09-19 01:30:07 +02:00
case AST_FCALL:
case AST_TCALL:
children_are_self_determined = true;
break;
further improved early width and sign detection in ast simplifier
2013-11-04 06:04:42 +01:00
default:
Various ast changes for early expression width detection (prep for constfold fixes)
2013-11-02 13:00:17 +01:00
width_hint = -1;
sign_hint = false;
}
further improved early width and sign detection in ast simplifier
2013-11-04 06:04:42 +01:00
if (detect_width_simple && width_hint < 0) {
further improved const function support
2014-06-07 00:02:05 +02:00
if (type == AST_REPLICATE)
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (children[0]->simplify(true, stage, -1, false) == true)
further improved const function support
2014-06-07 00:02:05 +02:00
did_something = true;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : children)
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (!child->basic_prep && child->simplify(false, stage, -1, false) == true)
Bugfix in recursive AST simplification
2014-03-05 19:45:33 +01:00
did_something = true;
further improved early width and sign detection in ast simplifier
2013-11-04 06:04:42 +01:00
detectSignWidth(width_hint, sign_hint);
Various ast changes for early expression width detection (prep for constfold fixes)
2013-11-02 13:00:17 +01:00
}
Added $past, $stable, $rose, $fell SVA functions
2016-09-19 01:30:07 +02:00
if (type == AST_FCALL && str == "\\$past")
detectSignWidth(width_hint, sign_hint);
Fixed handling of mixed real/int ternary expressions
2014-06-25 10:05:36 +02:00
if (type == AST_TERNARY) {
verilog: support recursive functions using ternary expressions This adds a mechanism for marking certain portions of elaboration as occurring within unevaluated ternary branches. To enable elaboration of the overall ternary, this also adds width detection for these unelaborated function calls.
2021-02-12 20:25:34 +01:00
if (width_hint < 0) {
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (!children[0]->basic_prep && children[0]->simplify(true, stage, -1, false))
verilog: support recursive functions using ternary expressions This adds a mechanism for marking certain portions of elaboration as occurring within unevaluated ternary branches. To enable elaboration of the overall ternary, this also adds width detection for these unelaborated function calls.
2021-02-12 20:25:34 +01:00
did_something = true;
bool backup_unevaluated_tern_branch = unevaluated_tern_branch;
AstNode *chosen = get_tern_choice().first;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
unevaluated_tern_branch = backup_unevaluated_tern_branch || chosen == children[2].get();
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (!children[1]->basic_prep && children[1]->simplify(false, stage, -1, false))
verilog: support recursive functions using ternary expressions This adds a mechanism for marking certain portions of elaboration as occurring within unevaluated ternary branches. To enable elaboration of the overall ternary, this also adds width detection for these unelaborated function calls.
2021-02-12 20:25:34 +01:00
did_something = true;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
unevaluated_tern_branch = backup_unevaluated_tern_branch || chosen == children[1].get();
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (!children[2]->basic_prep && children[2]->simplify(false, stage, -1, false))
verilog: support recursive functions using ternary expressions This adds a mechanism for marking certain portions of elaboration as occurring within unevaluated ternary branches. To enable elaboration of the overall ternary, this also adds width detection for these unelaborated function calls.
2021-02-12 20:25:34 +01:00
did_something = true;
unevaluated_tern_branch = backup_unevaluated_tern_branch;
detectSignWidth(width_hint, sign_hint);
}
Fixed handling of mixed real/int ternary expressions
2014-06-25 10:05:36 +02:00
int width_hint_left, width_hint_right;
bool sign_hint_left, sign_hint_right;
bool found_real_left, found_real_right;
children[1]->detectSignWidth(width_hint_left, sign_hint_left, &found_real_left);
children[2]->detectSignWidth(width_hint_right, sign_hint_right, &found_real_right);
if (found_real_left || found_real_right) {
child_1_is_self_determined = true;
child_2_is_self_determined = true;
}
}
Fixed handling of parameters and const functions in casex/casez pattern
2016-04-21 15:31:54 +02:00
if (type == AST_CONDX && children.size() > 0 && children.at(0)->type == AST_CONSTANT) {
for (auto &bit : children.at(0)->bits)
if (bit == State::Sz || bit == State::Sx)
bit = State::Sa;
}
if (type == AST_CONDZ && children.size() > 0 && children.at(0)->type == AST_CONSTANT) {
for (auto &bit : children.at(0)->bits)
if (bit == State::Sz)
bit = State::Sa;
}
AST simplifier: optimize constant AST_CASE nodes before recursively descending
2014-10-29 08:29:51 +01:00
if (const_fold && type == AST_CASE)
{
verilog: fix case expression sign and width handling - The case expression and case item expressions are extended to the maximum width among them, and are only interpreted as signed if all of them are signed - Add overall width and sign detection for AST_CASE - Add sign argument to genWidthRTLIL helper - Coverage for both const and non-const case statements
2021-03-25 19:06:05 +01:00
detectSignWidth(width_hint, sign_hint);
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (children[0]->simplify(const_fold, stage, width_hint, sign_hint)) { }
AST simplifier: optimize constant AST_CASE nodes before recursively descending
2014-10-29 08:29:51 +01:00
if (children[0]->type == AST_CONSTANT && children[0]->bits_only_01()) {
verilog: fix signedness when removing unreachable cases
2022-05-24 14:32:14 +02:00
children[0]->is_signed = sign_hint;
verilog: fix case expression sign and width handling - The case expression and case item expressions are extended to the maximum width among them, and are only interpreted as signed if all of them are signed - Add overall width and sign detection for AST_CASE - Add sign argument to genWidthRTLIL helper - Coverage for both const and non-const case statements
2021-03-25 19:06:05 +01:00
RTLIL::Const case_expr = children[0]->bitsAsConst(width_hint, sign_hint);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
std::vector<std::unique_ptr<AstNode>> new_children;
new_children.push_back(std::move(children[0]));
AST simplifier: optimize constant AST_CASE nodes before recursively descending
2014-10-29 08:29:51 +01:00
for (int i = 1; i < GetSize(children); i++) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto& child = children[i];
Fixed handling of parameters and const functions in casex/casez pattern
2016-04-21 15:31:54 +02:00
log_assert(child->type == AST_COND || child->type == AST_CONDX || child->type == AST_CONDZ);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& v : child->children) {
AST simplifier: optimize constant AST_CASE nodes before recursively descending
2014-10-29 08:29:51 +01:00
if (v->type == AST_DEFAULT)
goto keep_const_cond;
if (v->type == AST_BLOCK)
continue;
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (v->simplify(const_fold, stage, width_hint, sign_hint)) { }
AST simplifier: optimize constant AST_CASE nodes before recursively descending
2014-10-29 08:29:51 +01:00
if (v->type == AST_CONSTANT && v->bits_only_01()) {
verilog: fix case expression sign and width handling - The case expression and case item expressions are extended to the maximum width among them, and are only interpreted as signed if all of them are signed - Add overall width and sign detection for AST_CASE - Add sign argument to genWidthRTLIL helper - Coverage for both const and non-const case statements
2021-03-25 19:06:05 +01:00
RTLIL::Const case_item_expr = v->bitsAsConst(width_hint, sign_hint);
RTLIL::Const match = const_eq(case_expr, case_item_expr, sign_hint, sign_hint, 1);
rtlil: represent Const strings as std::string
2024-10-09 19:39:45 +02:00
log_assert(match.size() == 1);
if (match.front() == RTLIL::State::S1) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
// This is the only reachable case. Skip to the end
i = GetSize(children);
AST simplifier: optimize constant AST_CASE nodes before recursively descending
2014-10-29 08:29:51 +01:00
goto keep_const_cond;
}
continue;
}
goto keep_const_cond;
}
if (0)
keep_const_cond:
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
new_children.push_back(std::move(child));
AST simplifier: optimize constant AST_CASE nodes before recursively descending
2014-10-29 08:29:51 +01:00
}
new_children.swap(children);
}
}
verilog: Use proc memory writes in the frontend.
2021-02-23 16:48:29 +01:00
dict<std::string, pool<int>> backup_memwr_visible;
dict<std::string, pool<int>> final_memwr_visible;
if (type == AST_CASE && stage == 2) {
backup_memwr_visible = current_memwr_visible;
final_memwr_visible = current_memwr_visible;
}
initial import
2013-01-05 11:13:26 +01:00
// simplify all children first
// (iterate by index as e.g. auto wires can add new children in the process)
for (size_t i = 0; i < children.size(); i++) {
bool did_something_here = true;
Fix handling of defparam for when default_nettype is none Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-24 20:09:41 +01:00
bool backup_flag_autowire = flag_autowire;
verilog: support recursive functions using ternary expressions This adds a mechanism for marking certain portions of elaboration as occurring within unevaluated ternary branches. To enable elaboration of the overall ternary, this also adds width detection for these unelaborated function calls.
2021-02-12 20:25:34 +01:00
bool backup_unevaluated_tern_branch = unevaluated_tern_branch;
initial import
2013-01-05 11:13:26 +01:00
if ((type == AST_GENFOR || type == AST_FOR) && i >= 3)
break;
Various improvements in support for generate statements
2013-12-04 21:06:54 +01:00
if ((type == AST_GENIF || type == AST_GENCASE) && i >= 1)
initial import
2013-01-05 11:13:26 +01:00
break;
Fixed handling of unconditional generate blocks
2013-03-26 09:44:54 +01:00
if (type == AST_GENBLOCK)
break;
simplify: Skip AST_PRIMITIVE in AST_CELLARRAY Otherwise the `AST_PRIMITIVE` simplifies to the corresponding function and is no longer caught by the check for `AST_PRIMITIVE`s, raising an assertion error instead of an input error. Add bug4785.ys to tests/verilog to demonstrate.
2025-03-25 00:15:54 +01:00
if (type == AST_CELLARRAY && (children[i]->type == AST_CELL || children[i]->type == AST_PRIMITIVE))
simplify: Do not recursively simplify AST_CELL within AST_CELLARRAY Otherwise the AST_CELL simplification uses the wrong celltype before the AST_CELLARRAY simplification has a chance to unroll it and change it to the $array celltype.
2022-08-30 13:58:09 +02:00
continue;
Added support for local regs in named blocks
2013-12-04 09:10:16 +01:00
if (type == AST_BLOCK && !str.empty())
break;
Added support for verilog genblock[index].member syntax
2013-02-26 13:18:22 +01:00
if (type == AST_PREFIX && i >= 1)
break;
Fix handling of defparam for when default_nettype is none Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-24 20:09:41 +01:00
if (type == AST_DEFPARAM && i == 0)
flag_autowire = true;
verilog: support recursive functions using ternary expressions This adds a mechanism for marking certain portions of elaboration as occurring within unevaluated ternary branches. To enable elaboration of the overall ternary, this also adds width detection for these unelaborated function calls.
2021-02-12 20:25:34 +01:00
if (type == AST_TERNARY && i > 0 && !unevaluated_tern_branch) {
AstNode *chosen = get_tern_choice().first;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
unevaluated_tern_branch = chosen && chosen != children[i].get();
verilog: support recursive functions using ternary expressions This adds a mechanism for marking certain portions of elaboration as occurring within unevaluated ternary branches. To enable elaboration of the overall ternary, this also adds width detection for these unelaborated function calls.
2021-02-12 20:25:34 +01:00
}
initial import
2013-01-05 11:13:26 +01:00
while (did_something_here && i < children.size()) {
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
bool const_fold_here = const_fold;
Various ast changes for early expression width detection (prep for constfold fixes)
2013-11-02 13:00:17 +01:00
int width_hint_here = width_hint;
bool sign_hint_here = sign_hint;
further improved const function support
2014-06-07 00:02:05 +02:00
if (i == 0 && (type == AST_REPLICATE || type == AST_WIRE))
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
const_fold_here = true;
Fixed const folding in corner cases with parameters
2013-11-07 14:08:53 +01:00
if (type == AST_PARAMETER || type == AST_LOCALPARAM)
const_fold_here = true;
initial import
2013-01-05 11:13:26 +01:00
if (type == AST_BLOCK) {
current_block = this;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_block_child = children[i].get();
initial import
2013-01-05 11:13:26 +01:00
}
Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)
2013-03-31 11:19:11 +02:00
if ((type == AST_ALWAYS || type == AST_INITIAL) && children[i]->type == AST_BLOCK)
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_top_block = children[i].get();
further improved early width and sign detection in ast simplifier
2013-11-04 06:04:42 +01:00
if (i == 0 && child_0_is_self_determined)
width_hint_here = -1, sign_hint_here = false;
if (i == 1 && child_1_is_self_determined)
width_hint_here = -1, sign_hint_here = false;
Fixed handling of mixed real/int ternary expressions
2014-06-25 10:05:36 +02:00
if (i == 2 && child_2_is_self_determined)
width_hint_here = -1, sign_hint_here = false;
further improved early width and sign detection in ast simplifier
2013-11-04 06:04:42 +01:00
if (children_are_self_determined)
width_hint_here = -1, sign_hint_here = false;
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
did_something_here = children[i]->simplify(const_fold_here, stage, width_hint_here, sign_hint_here);
initial import
2013-01-05 11:13:26 +01:00
if (did_something_here)
did_something = true;
Fixed processing of initial values for block-local variables
2014-07-11 13:05:53 +02:00
}
if (stage == 2 && children[i]->type == AST_INITIAL && current_ast_mod != this) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_ast_mod->children.push_back(std::move(children[i]));
Fixed processing of initial values for block-local variables
2014-07-11 13:05:53 +02:00
children.erase(children.begin() + (i--));
did_something = true;
initial import
2013-01-05 11:13:26 +01:00
}
Fix handling of defparam for when default_nettype is none Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-24 20:09:41 +01:00
flag_autowire = backup_flag_autowire;
verilog: support recursive functions using ternary expressions This adds a mechanism for marking certain portions of elaboration as occurring within unevaluated ternary branches. To enable elaboration of the overall ternary, this also adds width detection for these unelaborated function calls.
2021-02-12 20:25:34 +01:00
unevaluated_tern_branch = backup_unevaluated_tern_branch;
verilog: Use proc memory writes in the frontend.
2021-02-23 16:48:29 +01:00
if (stage == 2 && type == AST_CASE) {
for (auto &x : current_memwr_visible) {
for (int y : x.second)
final_memwr_visible[x.first].insert(y);
}
current_memwr_visible = backup_memwr_visible;
}
initial import
2013-01-05 11:13:26 +01:00
}
for (auto &attr : attributes) {
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (attr.second->simplify(true, stage, -1, false))
Bugfix in recursive AST simplification
2014-03-05 19:45:33 +01:00
did_something = true;
initial import
2013-01-05 11:13:26 +01:00
}
verilog: Use proc memory writes in the frontend.
2021-02-23 16:48:29 +01:00
if (type == AST_CASE && stage == 2) {
current_memwr_visible = final_memwr_visible;
}
if (type == AST_ALWAYS && stage == 2) {
current_memwr_visible.clear();
current_memwr_count.clear();
}
initial import
2013-01-05 11:13:26 +01:00
further improved early width and sign detection in ast simplifier
2013-11-04 06:04:42 +01:00
if (reset_width_after_children) {
width_hint = backup_width_hint;
sign_hint = backup_sign_hint;
if (width_hint < 0)
detectSignWidth(width_hint, sign_hint);
}
initial import
2013-01-05 11:13:26 +01:00
current_block = backup_current_block;
current_block_child = backup_current_block_child;
current_top_block = backup_current_top_block;
Creating $meminit cells in verilog front-end
2015-02-14 10:49:30 +01:00
current_always = backup_current_always;
Avoid creation of bogus initial blocks for assert/assume in always @*
2016-09-06 17:34:42 +02:00
current_always_clocked = backup_current_always_clocked;
initial import
2013-01-05 11:13:26 +01:00
for (auto it = backup_scope.begin(); it != backup_scope.end(); it++) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
if (it->second == nullptr)
initial import
2013-01-05 11:13:26 +01:00
current_scope.erase(it->first);
else
current_scope[it->first] = it->second;
}
Resolve package types in interfaces (#3658) * Resolve package types in interfaces * Added test for resolving of package types in interfaces
2023-02-13 00:25:39 +01:00
if (type == AST_MODULE || type == AST_INTERFACE)
initial import
2013-01-05 11:13:26 +01:00
current_scope.clear();
Added defparam support to Verilog/AST frontend
2013-07-04 14:12:33 +02:00
// convert defparam nodes to cell parameters
Added support for hierarchical defparams
2016-11-15 13:35:19 +01:00
if (type == AST_DEFPARAM && !children.empty())
{
if (children[0]->type != AST_IDENTIFIER)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Module name in defparam contains non-constant expressions!\n");
Added support for hierarchical defparams
2016-11-15 13:35:19 +01:00
string modname, paramname = children[0]->str;
size_t pos = paramname.rfind('.');
while (pos != 0 && pos != std::string::npos)
{
modname = paramname.substr(0, pos);
if (current_scope.count(modname))
break;
pos = paramname.rfind('.', pos - 1);
}
Added defparam support to Verilog/AST frontend
2013-07-04 14:12:33 +02:00
if (pos == std::string::npos)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Can't find object for defparam `%s`!\n", RTLIL::unescape_id(paramname).c_str());
Added support for hierarchical defparams
2016-11-15 13:35:19 +01:00
paramname = "\\" + paramname.substr(pos+1);
if (current_scope.at(modname)->type != AST_CELL)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Defparam argument `%s . %s` does not match a cell!\n",
Various indenting fixes in AST front-end (mostly space vs tab issues) Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-04 10:19:32 +01:00
RTLIL::unescape_id(modname).c_str(), RTLIL::unescape_id(paramname).c_str());
Added support for hierarchical defparams
2016-11-15 13:35:19 +01:00
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto paraset = std::make_unique<AstNode>(location, AST_PARASET, children[1]->clone(), GetSize(children) > 2 ? children[2]->clone() : nullptr);
Added support for hierarchical defparams
2016-11-15 13:35:19 +01:00
paraset->str = paramname;
AstNode *cell = current_scope.at(modname);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
cell->children.insert(cell->children.begin() + 1, std::move(paraset));
Added support for hierarchical defparams
2016-11-15 13:35:19 +01:00
delete_children();
Added defparam support to Verilog/AST frontend
2013-07-04 14:12:33 +02:00
}
sv: Switch parser to glr, prep for typedef Signed-off-by: David Shah <dave@ds0.me>
2019-09-19 21:43:13 +02:00
// resolve typedefs
if (type == AST_TYPEDEF) {
log_assert(children.size() == 1);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto& type_node = children[0];
Generalise structs and add support for packed unions.
2020-05-12 15:25:33 +02:00
log_assert(type_node->type == AST_WIRE || type_node->type == AST_MEMORY || type_node->type == AST_STRUCT || type_node->type == AST_UNION);
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (type_node->simplify(const_fold, stage, width_hint, sign_hint)) {
sv: Add support for memory typedefs Signed-off-by: David Shah <dave@ds0.me>
2019-09-20 12:39:15 +02:00
did_something = true;
Implement SV structs.
2020-05-08 15:40:49 +02:00
}
log_assert(!type_node->is_custom_type);
sv: Switch parser to glr, prep for typedef Signed-off-by: David Shah <dave@ds0.me>
2019-09-19 21:43:13 +02:00
}
sv: Fix typedef parameters Signed-off-by: David Shah <dave@ds0.me>
2019-09-19 22:07:20 +02:00
// resolve types of wires
sv: Add support for memories of a typedef Signed-off-by: David Shah <dave@ds0.me>
2019-09-20 12:46:37 +02:00
if (type == AST_WIRE || type == AST_MEMORY) {
sv: Switch parser to glr, prep for typedef Signed-off-by: David Shah <dave@ds0.me>
2019-09-19 21:43:13 +02:00
if (is_custom_type) {
sv: Add support for memories of a typedef Signed-off-by: David Shah <dave@ds0.me>
2019-09-20 12:46:37 +02:00
log_assert(children.size() >= 1);
sv: Switch parser to glr, prep for typedef Signed-off-by: David Shah <dave@ds0.me>
2019-09-19 21:43:13 +02:00
log_assert(children[0]->type == AST_WIRETYPE);
Implement SV structs.
2020-05-08 15:40:49 +02:00
auto type_name = children[0]->str;
if (!current_scope.count(type_name)) {
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Unknown identifier `%s' used as type name\n", type_name.c_str());
Implement SV structs.
2020-05-08 15:40:49 +02:00
}
AstNode *resolved_type_node = current_scope.at(type_name);
if (resolved_type_node->type != AST_TYPEDEF)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("`%s' does not name a type\n", type_name.c_str());
Implement SV structs.
2020-05-08 15:40:49 +02:00
log_assert(resolved_type_node->children.size() == 1);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto& template_node = resolved_type_node->children[0];
Implement SV structs.
2020-05-08 15:40:49 +02:00
Resolve multiple dimensions defined in stages with typedef
2024-01-01 01:18:00 +01:00
// Resolve the typedef from the bottom up, recursing within the current
// block of code. Defer further simplification until the complete type is
// resolved.
while (template_node->is_custom_type && template_node->simplify(const_fold, stage, width_hint, sign_hint)) {};
Implement SV structs.
2020-05-08 15:40:49 +02:00
Corrected handling of nested typedefs of struct/union This also corrects shadowing of constants in struct/union types.
2023-01-29 20:22:00 +01:00
if (!str.empty() && str[0] == '\\' && (template_node->type == AST_STRUCT || template_node->type == AST_UNION)) {
// replace instance with wire representing the packed structure
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
newNode = make_packed_struct(template_node.get(), str, attributes);
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode->set_attribute(ID::wiretype, mkconst_str(newNode->location, resolved_type_node->str));
Fix input/output attributes when resolving typedef of wire Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-09 09:53:00 +02:00
// add original input/output attribute to resolved wire
newNode->is_input = this->is_input;
newNode->is_output = this->is_output;
Implement SV structs.
2020-05-08 15:40:49 +02:00
current_scope[str] = this;
goto apply_newNode;
}
Resolve multiple dimensions defined in stages with typedef
2024-01-01 01:18:00 +01:00
// Prepare replacement node.
newNode = template_node->clone();
newNode->str = str;
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode->set_attribute(ID::wiretype, mkconst_str(newNode->location, resolved_type_node->str));
Resolve multiple dimensions defined in stages with typedef
2024-01-01 01:18:00 +01:00
newNode->is_input = is_input;
newNode->is_output = is_output;
newNode->is_wand = is_wand;
newNode->is_wor = is_wor;
for (auto &pair : attributes)
newNode->set_attribute(pair.first, pair.second->clone());
sv: Switch parser to glr, prep for typedef Signed-off-by: David Shah <dave@ds0.me>
2019-09-19 21:43:13 +02:00
Resolve multiple dimensions defined in stages with typedef
2024-01-01 01:18:00 +01:00
// if an enum then add attributes to support simulator tracing
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
newNode->annotateTypedEnums(template_node.get());
Implement SV structs.
2020-05-08 15:40:49 +02:00
Resolve multiple dimensions defined in stages with typedef
2024-01-01 01:18:00 +01:00
bool add_packed_dimensions = (type == AST_WIRE && GetSize(children) > 1) || (type == AST_MEMORY && GetSize(children) > 2);
Implement SV structs.
2020-05-08 15:40:49 +02:00
Resolve multiple dimensions defined in stages with typedef
2024-01-01 01:18:00 +01:00
// Cannot add packed dimensions if unpacked dimensions are already specified.
if (add_packed_dimensions && newNode->type == AST_MEMORY)
input_error("Cannot extend unpacked type `%s' with packed dimensions\n", type_name.c_str());
sv: Add support for memories of a typedef Signed-off-by: David Shah <dave@ds0.me>
2019-09-20 12:46:37 +02:00
Resolve multiple dimensions defined in stages with typedef
2024-01-01 01:18:00 +01:00
// Add packed dimensions.
if (add_packed_dimensions) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto& packed = children[1];
Resolve multiple dimensions defined in stages with typedef
2024-01-01 01:18:00 +01:00
if (newNode->children.empty())
newNode->children.insert(newNode->children.begin(), packed->clone());
else
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
prepend_ranges(newNode->children[0], packed.get());
Resolve multiple dimensions defined in stages with typedef
2024-01-01 01:18:00 +01:00
}
partial rebase of PeterCrozier's enum work onto current master I tried to keep only the enum-related changes, and minimize the diff. (The original commit also had a lot of work done to get typedefs working, but yosys has diverged quite a bit since the 2018-03-09 commit, with a new typedef implementation.) I did not include the import related changes either. Original commit: "Initial implementation of enum, typedef, import. Still a WIP." https://github.com/PeterCrozier/yosys/commit/881833aa738e7404987646ea8076284e911fce3f
2018-03-09 13:47:11 +01:00
Resolve multiple dimensions defined in stages with typedef
2024-01-01 01:18:00 +01:00
// Add unpacked dimensions.
if (type == AST_MEMORY) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto& unpacked = children.back();
Resolve multiple dimensions defined in stages with typedef
2024-01-01 01:18:00 +01:00
if (GetSize(newNode->children) < 2)
newNode->children.push_back(unpacked->clone());
else
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
prepend_ranges(newNode->children[1], unpacked.get());
Resolve multiple dimensions defined in stages with typedef
2024-01-01 01:18:00 +01:00
newNode->type = type;
sv: Add support for memories of a typedef Signed-off-by: David Shah <dave@ds0.me>
2019-09-20 12:46:37 +02:00
}
Resolve multiple dimensions defined in stages with typedef
2024-01-01 01:18:00 +01:00
// Prepare to generate dimensions metadata for the resolved type.
newNode->dimensions.clear();
newNode->unpacked_dimensions = 0;
goto apply_newNode;
sv: Switch parser to glr, prep for typedef Signed-off-by: David Shah <dave@ds0.me>
2019-09-19 21:43:13 +02:00
}
}
sv: Fix typedef parameters Signed-off-by: David Shah <dave@ds0.me>
2019-09-19 22:07:20 +02:00
// resolve types of parameters
if (type == AST_LOCALPARAM || type == AST_PARAMETER) {
if (is_custom_type) {
Resolve multiple dimensions defined in stages with typedef
2024-01-01 01:18:00 +01:00
log_assert(children.size() >= 2);
sv: Fix typedef parameters Signed-off-by: David Shah <dave@ds0.me>
2019-09-19 22:07:20 +02:00
log_assert(children[1]->type == AST_WIRETYPE);
Resolve struct member multiple dimensions defined in stages with typedef
2024-01-05 19:29:06 +01:00
// Pretend it's just a wire in order to resolve the type in the code block above.
Resolve multiple dimensions defined in stages with typedef
2024-01-01 01:18:00 +01:00
AstNodeType param_type = type;
type = AST_WIRE;
frontends/ast: More usage of auto For consistency.
2025-08-08 07:10:16 +02:00
auto expr = std::move(children.front());
Resolve multiple dimensions defined in stages with typedef
2024-01-01 01:18:00 +01:00
children.erase(children.begin());
Resolve struct member multiple dimensions defined in stages with typedef
2024-01-05 19:29:06 +01:00
while (is_custom_type && simplify(const_fold, stage, width_hint, sign_hint)) {};
Resolve multiple dimensions defined in stages with typedef
2024-01-01 01:18:00 +01:00
type = param_type;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
children.insert(children.begin(), std::move(expr));
Resolve struct member multiple dimensions defined in stages with typedef
2024-01-05 19:29:06 +01:00
Resolve multiple dimensions defined in stages with typedef
2024-01-01 01:18:00 +01:00
if (children[1]->type == AST_MEMORY)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("unpacked array type `%s' cannot be used for a parameter\n", children[1]->str.c_str());
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
fixup_hierarchy_flags();
sv: Add support for memory typedefs Signed-off-by: David Shah <dave@ds0.me>
2019-09-20 12:39:15 +02:00
did_something = true;
sv: Fix typedef parameters Signed-off-by: David Shah <dave@ds0.me>
2019-09-19 22:07:20 +02:00
}
log_assert(!is_custom_type);
partial rebase of PeterCrozier's enum work onto current master I tried to keep only the enum-related changes, and minimize the diff. (The original commit also had a lot of work done to get typedefs working, but yosys has diverged quite a bit since the 2018-03-09 commit, with a new typedef implementation.) I did not include the import related changes either. Original commit: "Initial implementation of enum, typedef, import. Still a WIP." https://github.com/PeterCrozier/yosys/commit/881833aa738e7404987646ea8076284e911fce3f
2018-03-09 13:47:11 +01:00
}
sv: Fix typedef parameters Signed-off-by: David Shah <dave@ds0.me>
2019-09-19 22:07:20 +02:00
Added support for verilog genblock[index].member syntax
2013-02-26 13:18:22 +01:00
// resolve constant prefixes
if (type == AST_PREFIX) {
if (children[0]->type != AST_CONSTANT) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
// dumpAst(nullptr, "> ");
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Index in generate block prefix syntax is not constant!\n");
Added support for verilog genblock[index].member syntax
2013-02-26 13:18:22 +01:00
}
Fixed multi-level prefix resolving
2015-09-22 20:52:02 +02:00
if (children[1]->type == AST_PREFIX)
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
children[1]->simplify(const_fold, stage, width_hint, sign_hint);
Using log_assert() instead of assert()
2014-07-28 11:08:55 +02:00
log_assert(children[1]->type == AST_IDENTIFIER);
Added support for verilog genblock[index].member syntax
2013-02-26 13:18:22 +01:00
newNode = children[1]->clone();
Another name resolution bugfix for generate blocks
2013-11-20 13:57:40 +01:00
const char *second_part = children[1]->str.c_str();
if (second_part[0] == '\\')
second_part++;
newNode->str = stringf("%s[%d].%s", str.c_str(), children[0]->integer, second_part);
Added support for verilog genblock[index].member syntax
2013-02-26 13:18:22 +01:00
goto apply_newNode;
}
Added constant size expression support of sized constants
2014-02-01 13:50:23 +01:00
// evaluate TO_BITS nodes
if (type == AST_TO_BITS) {
if (children[0]->type != AST_CONSTANT)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Left operand of to_bits expression is not constant!\n");
Added constant size expression support of sized constants
2014-02-01 13:50:23 +01:00
if (children[1]->type != AST_CONSTANT)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Right operand of to_bits expression is not constant!\n");
Added constant size expression support of sized constants
2014-02-01 13:50:23 +01:00
RTLIL::Const new_value = children[1]->bitsAsConst(children[0]->bitsAsConst().as_int(), children[1]->is_signed);
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = mkconst_bits(location, new_value.to_bits(), children[1]->is_signed);
Added constant size expression support of sized constants
2014-02-01 13:50:23 +01:00
goto apply_newNode;
}
initial import
2013-01-05 11:13:26 +01:00
// annotate constant ranges
if (type == AST_RANGE) {
bool old_range_valid = range_valid;
range_valid = false;
Added support for "upto" wires to Verilog front- and back-end
2014-07-28 14:25:03 +02:00
range_swapped = false;
initial import
2013-01-05 11:13:26 +01:00
range_left = -1;
range_right = 0;
Using log_assert() instead of assert()
2014-07-28 11:08:55 +02:00
log_assert(children.size() >= 1);
initial import
2013-01-05 11:13:26 +01:00
if (children[0]->type == AST_CONSTANT) {
range_valid = true;
range_left = children[0]->integer;
if (children.size() == 1)
range_right = range_left;
}
if (children.size() >= 2) {
if (children[1]->type == AST_CONSTANT)
range_right = children[1]->integer;
else
range_valid = false;
}
if (old_range_valid != range_valid)
did_something = true;
ast: swap range regardless of range_left >= 0
2020-05-04 21:18:20 +02:00
if (range_valid && range_right > range_left) {
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
std::swap(range_left, range_right);
Added support for "upto" wires to Verilog front- and back-end
2014-07-28 14:25:03 +02:00
range_swapped = true;
initial import
2013-01-05 11:13:26 +01:00
}
}
// annotate wires with their ranges
if (type == AST_WIRE) {
if (children.size() > 0) {
if (children[0]->range_valid) {
if (!range_valid)
did_something = true;
range_valid = true;
Added support for "upto" wires to Verilog front- and back-end
2014-07-28 14:25:03 +02:00
range_swapped = children[0]->range_swapped;
initial import
2013-01-05 11:13:26 +01:00
range_left = children[0]->range_left;
range_right = children[0]->range_right;
Add force_downto and force_upto wire attributes. Fixes #2058.
2020-05-18 18:15:03 +02:00
bool force_upto = false, force_downto = false;
if (attributes.count(ID::force_upto)) {
frontends/ast: More usage of auto For consistency.
2025-08-08 07:10:16 +02:00
auto* val = attributes[ID::force_upto].get();
Add force_downto and force_upto wire attributes. Fixes #2058.
2020-05-18 18:15:03 +02:00
if (val->type != AST_CONSTANT)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Attribute `force_upto' with non-constant value!\n");
Add force_downto and force_upto wire attributes. Fixes #2058.
2020-05-18 18:15:03 +02:00
force_upto = val->asAttrConst().as_bool();
}
if (attributes.count(ID::force_downto)) {
frontends/ast: More usage of auto For consistency.
2025-08-08 07:10:16 +02:00
auto* val = attributes[ID::force_downto].get();
Add force_downto and force_upto wire attributes. Fixes #2058.
2020-05-18 18:15:03 +02:00
if (val->type != AST_CONSTANT)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Attribute `force_downto' with non-constant value!\n");
Add force_downto and force_upto wire attributes. Fixes #2058.
2020-05-18 18:15:03 +02:00
force_downto = val->asAttrConst().as_bool();
}
if (force_upto && force_downto)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Attributes `force_downto' and `force_upto' cannot be both set!\n");
Add force_downto and force_upto wire attributes. Fixes #2058.
2020-05-18 18:15:03 +02:00
if ((force_upto && !range_swapped) || (force_downto && range_swapped)) {
std::swap(range_left, range_right);
range_swapped = force_upto;
}
simplify: fix single_bit_vector memory leak
2025-06-04 10:32:03 +02:00
if (range_left == range_right && !attributes.count(ID::single_bit_vector))
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
set_attribute(ID::single_bit_vector, mkconst_int(location, 1, false));
initial import
2013-01-05 11:13:26 +01:00
}
} else {
if (!range_valid)
did_something = true;
range_valid = true;
Added support for "upto" wires to Verilog front- and back-end
2014-07-28 14:25:03 +02:00
range_swapped = false;
initial import
2013-01-05 11:13:26 +01:00
range_left = 0;
range_right = 0;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
attributes.erase(ID::single_bit_vector);
initial import
2013-01-05 11:13:26 +01:00
}
}
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
// Resolve packed and unpacked ranges in declarations.
if ((type == AST_WIRE || type == AST_MEMORY) && dimensions.empty()) {
if (!children.empty()) {
// Unpacked ranges first, then packed ranges.
for (int i = std::min(GetSize(children), 2) - 1; i >= 0; i--) {
if (children[i]->type == AST_MULTIRANGE) {
int width = 1;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& range : children[i]->children) {
width *= add_dimension(this, range.get());
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
if (i) unpacked_dimensions++;
}
int left = width - 1, right = 0;
if (i)
std::swap(left, right);
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto loc = children[i]->location;
children[i] = std::make_unique<AstNode>(loc, AST_RANGE, mkconst_int(loc, left, true), mkconst_int(loc, right, true));
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
fixup_hierarchy_flags();
did_something = true;
} else if (children[i]->type == AST_RANGE) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
add_dimension(this, children[i].get());
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
if (i) unpacked_dimensions++;
}
}
} else {
// 1 bit signal: bit, logic or reg
dimensions.push_back({ 0, 1, false });
Added AST_MULTIRANGE (arrays with more than 1 dimension)
2014-08-06 15:43:46 +02:00
}
}
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
// Resolve multidimensional array access.
if (type == AST_IDENTIFIER && !basic_prep && id2ast && (id2ast->type == AST_WIRE || id2ast->type == AST_MEMORY) &&
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
children.size() > 0 && (children[0]->type == AST_RANGE || children[0]->type == AST_MULTIRANGE))
Added AST_MULTIRANGE (arrays with more than 1 dimension)
2014-08-06 15:43:46 +02:00
{
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
int dims_sel = children[0]->type == AST_MULTIRANGE ? children[0]->children.size() : 1;
// Save original number of dimensions for $size() etc.
integer = dims_sel;
// Split access into unpacked and packed parts.
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
std::unique_ptr<AstNode> unpacked_range = nullptr;
std::unique_ptr<AstNode> packed_range = nullptr;
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
if (id2ast->unpacked_dimensions) {
if (id2ast->unpacked_dimensions > 1) {
// Flattened range for access to unpacked dimensions.
unpacked_range = make_index_range(id2ast, true);
} else {
// Index into one-dimensional unpacked part; unlink simple range node.
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto& range = children[0]->type == AST_MULTIRANGE ? children[0]->children[0] : children[0];
unpacked_range = std::move(range);
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
range = nullptr;
}
}
Added AST_MULTIRANGE (arrays with more than 1 dimension)
2014-08-06 15:43:46 +02:00
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
if (dims_sel > id2ast->unpacked_dimensions) {
if (GetSize(id2ast->dimensions) - id2ast->unpacked_dimensions > 1) {
// Flattened range for access to packed dimensions.
packed_range = make_index_range(id2ast, false);
} else {
// Index into one-dimensional packed part; unlink simple range node.
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto& range = children[0]->type == AST_MULTIRANGE ? children[0]->children[dims_sel - 1] : children[0];
packed_range = std::move(range);
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
range = nullptr;
}
Added AST_MULTIRANGE (arrays with more than 1 dimension)
2014-08-06 15:43:46 +02:00
}
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
children.clear();
Added AST_MULTIRANGE (arrays with more than 1 dimension)
2014-08-06 15:43:46 +02:00
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
if (unpacked_range)
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
children.push_back(std::move(unpacked_range));
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
if (packed_range)
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
children.push_back(std::move(packed_range));
Added AST_MULTIRANGE (arrays with more than 1 dimension)
2014-08-06 15:43:46 +02:00
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
fixup_hierarchy_flags();
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
basic_prep = true;
Added AST_MULTIRANGE (arrays with more than 1 dimension)
2014-08-06 15:43:46 +02:00
did_something = true;
}
Various fixes for correct parameter support
2013-11-07 09:58:15 +01:00
// trim/extend parameters
partial rebase of PeterCrozier's enum work onto current master I tried to keep only the enum-related changes, and minimize the diff. (The original commit also had a lot of work done to get typedefs working, but yosys has diverged quite a bit since the 2018-03-09 commit, with a new typedef implementation.) I did not include the import related changes either. Original commit: "Initial implementation of enum, typedef, import. Still a WIP." https://github.com/PeterCrozier/yosys/commit/881833aa738e7404987646ea8076284e911fce3f
2018-03-09 13:47:11 +01:00
if (type == AST_PARAMETER || type == AST_LOCALPARAM || type == AST_ENUM_ITEM) {
Added handling of real-valued parameters/localparams
2014-06-14 12:00:47 +02:00
if (children.size() > 1 && children[1]->type == AST_RANGE) {
improved (fixed) conversion of real values to bit vectors
2014-06-14 20:38:05 +02:00
if (!children[1]->range_valid)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Non-constant width range on parameter decl.\n");
Fixed handling of parameters with reversed range
2015-06-08 14:03:06 +02:00
int width = std::abs(children[1]->range_left - children[1]->range_right) + 1;
Added handling of real-valued parameters/localparams
2014-06-14 12:00:47 +02:00
if (children[0]->type == AST_REALVALUE) {
improved (fixed) conversion of real values to bit vectors
2014-06-14 20:38:05 +02:00
RTLIL::Const constvalue = children[0]->realAsConst(width);
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
log_file_warning(*location.begin.filename, location.begin.line, "converting real value %e to binary %s.\n",
Various indenting fixes in AST front-end (mostly space vs tab issues) Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-04 10:19:32 +01:00
children[0]->realvalue, log_signal(constvalue));
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
children[0] = mkconst_bits(location, constvalue.to_bits(), sign_hint);
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
fixup_hierarchy_flags();
Added handling of real-valued parameters/localparams
2014-06-14 12:00:47 +02:00
did_something = true;
}
if (children[0]->type == AST_CONSTANT) {
if (width != int(children[0]->bits.size())) {
RTLIL::SigSpec sig(children[0]->bits);
sig.extend_u0(width, children[0]->is_signed);
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
children[0] = mkconst_bits(location, sig.as_const().to_bits(), is_signed);
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
fixup_hierarchy_flags();
Added handling of real-valued parameters/localparams
2014-06-14 12:00:47 +02:00
}
children[0]->is_signed = is_signed;
}
Fixed part selects of parameters
2014-07-28 16:45:26 +02:00
range_valid = true;
range_swapped = children[1]->range_swapped;
range_left = children[1]->range_left;
range_right = children[1]->range_right;
Added handling of real-valued parameters/localparams
2014-06-14 12:00:47 +02:00
} else
if (children.size() > 1 && children[1]->type == AST_REALVALUE && children[0]->type == AST_CONSTANT) {
double as_realvalue = children[0]->asReal(sign_hint);
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
children[0] = std::make_unique<AstNode>(location, AST_REALVALUE);
Added handling of real-valued parameters/localparams
2014-06-14 12:00:47 +02:00
children[0]->realvalue = as_realvalue;
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
fixup_hierarchy_flags();
Added handling of real-valued parameters/localparams
2014-06-14 12:00:47 +02:00
did_something = true;
Various fixes for correct parameter support
2013-11-07 09:58:15 +01:00
}
}
Implement SV structs.
2020-05-08 15:40:49 +02:00
if (type == AST_IDENTIFIER && !basic_prep) {
// check if a plausible struct member sss.mmmm
Correct hierarchical path names for structs and unions
2024-01-04 17:22:07 +01:00
if (!str.empty() && str[0] == '\\' && current_scope.count(str)) {
auto item_node = current_scope[str];
if (item_node->type == AST_STRUCT_ITEM || item_node->type == AST_STRUCT || item_node->type == AST_UNION) {
// Traverse any hierarchical path until the full name for the referenced struct/union is found.
std::string sname;
bool found_sname = false;
for (std::string::size_type pos = 0; (pos = str.find('.', pos)) != std::string::npos; pos++) {
sname = str.substr(0, pos);
if (current_scope.count(sname)) {
auto stype = current_scope[sname]->type;
if (stype == AST_WIRE || stype == AST_PARAMETER || stype == AST_LOCALPARAM) {
found_sname = true;
break;
}
}
}
if (found_sname) {
Implement SV structs.
2020-05-08 15:40:49 +02:00
// structure member, rewrite this node to reference the packed struct wire
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
auto range = make_index_range(item_node);
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = std::make_unique<AstNode>(location, AST_IDENTIFIER, std::move(range));
Implement SV structs.
2020-05-08 15:40:49 +02:00
newNode->str = sname;
Support for data and array queries on struct/union item expressions For now, $bits, $left, $right, $low, $high, and $size are supported.
2023-02-09 19:27:51 +01:00
// save type and original number of dimensions for $size() etc.
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
newNode->set_attribute(ID::wiretype, item_node->clone());
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
if (!item_node->dimensions.empty() && children.size() > 0) {
Support for data and array queries on struct/union item expressions For now, $bits, $left, $right, $low, $high, and $size are supported.
2023-02-09 19:27:51 +01:00
if (children[0]->type == AST_RANGE)
newNode->integer = 1;
else if (children[0]->type == AST_MULTIRANGE)
newNode->integer = children[0]->children.size();
}
Implement SV structs.
2020-05-08 15:40:49 +02:00
newNode->basic_prep = true;
sv: fix two struct access bugs - preserve signedness of struct members - fix initial width detection of struct members (e.g., in case expressions)
2021-06-22 16:39:57 +02:00
if (item_node->is_signed)
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = std::make_unique<AstNode>(location, AST_TO_SIGNED, std::move(newNode));
Implement SV structs.
2020-05-08 15:40:49 +02:00
goto apply_newNode;
}
}
}
}
Support packed arrays in struct/union.
2020-06-07 19:28:45 +02:00
// annotate identifiers using scope resolution and create auto-wires as needed
initial import
2013-01-05 11:13:26 +01:00
if (type == AST_IDENTIFIER) {
if (current_scope.count(str) == 0) {
ast: Fix handling of identifiers in the global scope Signed-off-by: David Shah <dave@ds0.me>
2020-04-16 11:27:59 +02:00
AstNode *current_scope_ast = (current_ast_mod == nullptr) ? current_ast : current_ast_mod;
verilog: check for module scope identifiers during width detection The recent fix for case expression width detection causes the width of the expressions to be queried before they are simplified. Because the logic supporting module scope identifiers only existed in simplify, looking them up would fail during width detection. This moves the logic to a common helper used in both simplify() and detectSignWidthWorker().
2021-06-05 22:21:09 +02:00
str = try_pop_module_prefix();
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& node : current_scope_ast->children) {
partial rebase of PeterCrozier's enum work onto current master I tried to keep only the enum-related changes, and minimize the diff. (The original commit also had a lot of work done to get typedefs working, but yosys has diverged quite a bit since the 2018-03-09 commit, with a new typedef implementation.) I did not include the import related changes either. Original commit: "Initial implementation of enum, typedef, import. Still a WIP." https://github.com/PeterCrozier/yosys/commit/881833aa738e7404987646ea8076284e911fce3f
2018-03-09 13:47:11 +01:00
//log("looking at mod scope child %s\n", type2str(node->type).c_str());
switch (node->type) {
case AST_PARAMETER:
case AST_LOCALPARAM:
case AST_WIRE:
case AST_AUTOWIRE:
case AST_GENVAR:
case AST_MEMORY:
case AST_FUNCTION:
case AST_TASK:
case AST_DPI_FUNCTION:
//log("found child %s, %s\n", type2str(node->type).c_str(), node->str.c_str());
fix bug introduced by not taking all of PeterCrozier's changes in 16ea4ea6 The if(str == node->str) is in fact necessary (otherwise causes generate for in Multiplier_2D in tests/simple/multiplier.v to fail with error message "Right hand side of 3rd expression of generate for-loop is not constant!"). Note: in PeterCrozier's implementation, the break only breaks out of the switch-case, not the outer for loop.
2020-01-17 07:21:09 +01:00
if (str == node->str) {
Comment out log()
2020-02-28 01:53:49 +01:00
//log("add %s, type %s to scope\n", str.c_str(), type2str(node->type).c_str());
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_scope[node->str] = node.get();
fix bug introduced by not taking all of PeterCrozier's changes in 16ea4ea6 The if(str == node->str) is in fact necessary (otherwise causes generate for in Multiplier_2D in tests/simple/multiplier.v to fail with error message "Right hand side of 3rd expression of generate for-loop is not constant!"). Note: in PeterCrozier's implementation, the break only breaks out of the switch-case, not the outer for loop.
2020-01-17 07:21:09 +01:00
}
initial import
2013-01-05 11:13:26 +01:00
break;
partial rebase of PeterCrozier's enum work onto current master I tried to keep only the enum-related changes, and minimize the diff. (The original commit also had a lot of work done to get typedefs working, but yosys has diverged quite a bit since the 2018-03-09 commit, with a new typedef implementation.) I did not include the import related changes either. Original commit: "Initial implementation of enum, typedef, import. Still a WIP." https://github.com/PeterCrozier/yosys/commit/881833aa738e7404987646ea8076284e911fce3f
2018-03-09 13:47:11 +01:00
case AST_ENUM:
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_scope[node->str] = node.get();
for (auto& enum_node : node->children) {
partial rebase of PeterCrozier's enum work onto current master I tried to keep only the enum-related changes, and minimize the diff. (The original commit also had a lot of work done to get typedefs working, but yosys has diverged quite a bit since the 2018-03-09 commit, with a new typedef implementation.) I did not include the import related changes either. Original commit: "Initial implementation of enum, typedef, import. Still a WIP." https://github.com/PeterCrozier/yosys/commit/881833aa738e7404987646ea8076284e911fce3f
2018-03-09 13:47:11 +01:00
log_assert(enum_node->type==AST_ENUM_ITEM);
if (str == enum_node->str) {
add attributes for enumerated values in ilang - information also useful for strongly-typed enums (not implemented) - resolves enum values in ilang part of #1594 - still need to output enums to VCD (or better yet FST) files
2020-02-03 07:12:24 +01:00
//log("\nadding enum item %s to scope\n", str.c_str());
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_scope[str] = enum_node.get();
partial rebase of PeterCrozier's enum work onto current master I tried to keep only the enum-related changes, and minimize the diff. (The original commit also had a lot of work done to get typedefs working, but yosys has diverged quite a bit since the 2018-03-09 commit, with a new typedef implementation.) I did not include the import related changes either. Original commit: "Initial implementation of enum, typedef, import. Still a WIP." https://github.com/PeterCrozier/yosys/commit/881833aa738e7404987646ea8076284e911fce3f
2018-03-09 13:47:11 +01:00
}
}
break;
default:
initial import
2013-01-05 11:13:26 +01:00
break;
}
}
}
if (current_scope.count(str) == 0) {
ast: Fix handling of identifiers in the global scope Signed-off-by: David Shah <dave@ds0.me>
2020-04-16 11:27:59 +02:00
if (current_ast_mod == nullptr) {
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Identifier `%s' is implicitly declared outside of a module.\n", str.c_str());
ast: Fix handling of identifiers in the global scope Signed-off-by: David Shah <dave@ds0.me>
2020-04-16 11:27:59 +02:00
} else if (flag_autowire || str == "\\$global_clock") {
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto auto_wire = std::make_unique<AstNode>(location, AST_AUTOWIRE);
Fixes related to handling of autowires and upto-ranges, fixes #814 Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 18:40:11 +01:00
auto_wire->str = str;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_scope[str] = auto_wire.get();
current_ast_mod->children.push_back(std::move(auto_wire));
Fixes related to handling of autowires and upto-ranges, fixes #814 Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 18:40:11 +01:00
did_something = true;
} else {
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str.c_str());
Fixes related to handling of autowires and upto-ranges, fixes #814 Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 18:40:11 +01:00
}
initial import
2013-01-05 11:13:26 +01:00
}
Bugfix in recursive AST simplification
2014-03-05 19:45:33 +01:00
if (id2ast != current_scope[str]) {
id2ast = current_scope[str];
did_something = true;
}
initial import
2013-01-05 11:13:26 +01:00
}
Implemented part/bit select on memory read
2013-11-20 10:51:32 +01:00
// split memory access with bit select to individual statements
mem2reg: tolerate out of bounds constant accesses This brings the mem2reg behavior in line with the nomem2reg behavior.
2021-05-27 00:22:31 +02:00
if (type == AST_IDENTIFIER && children.size() == 2 && children[0]->type == AST_RANGE && children[1]->type == AST_RANGE && !in_lvalue && stage == 2)
Implemented part/bit select on memory read
2013-11-20 10:51:32 +01:00
{
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
if (id2ast == nullptr || id2ast->type != AST_MEMORY || children[0]->children.size() != 1)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Invalid bit-select on memory access!\n");
Implemented part/bit select on memory read
2013-11-20 10:51:32 +01:00
int mem_width, mem_size, addr_bits;
id2ast->meminfo(mem_width, mem_size, addr_bits);
Fixed bug with memories that do not have a down-to-zero data width
2016-08-22 14:27:46 +02:00
int data_range_left = id2ast->children[0]->range_left;
int data_range_right = id2ast->children[0]->range_right;
Fix mem2reg handling of memories with upto data ports, fixes #888 Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-21 22:19:17 +01:00
if (id2ast->children[0]->range_swapped)
std::swap(data_range_left, data_range_right);
Implemented part/bit select on memory read
2013-11-20 10:51:32 +01:00
std::stringstream sstr;
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
sstr << "$mem2bits$" << str << "$" << RTLIL::encode_filename(*location.begin.filename) << ":" << location.begin.line << "$" << (autoidx++);
Implemented part/bit select on memory read
2013-11-20 10:51:32 +01:00
std::string wire_id = sstr.str();
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto wire_owned = std::make_unique<AstNode>(location, AST_WIRE, std::make_unique<AstNode>(location, AST_RANGE, mkconst_int(location, data_range_left, true), mkconst_int(location, data_range_right, true)));
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto* wire = wire_owned.get();
current_ast_mod->children.push_back(std::move(wire_owned));
Implemented part/bit select on memory read
2013-11-20 10:51:32 +01:00
wire->str = wire_id;
if (current_block)
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
wire->set_attribute(ID::nosync, AstNode::mkconst_int(location, 1, false));
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (wire->simplify(true, 1, -1, false)) { }
Implemented part/bit select on memory read
2013-11-20 10:51:32 +01:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto data = clone();
Implemented part/bit select on memory read
2013-11-20 10:51:32 +01:00
data->children.pop_back();
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto assign = std::make_unique<AstNode>(location, AST_ASSIGN_EQ, std::make_unique<AstNode>(location, AST_IDENTIFIER), std::move(data));
Implemented part/bit select on memory read
2013-11-20 10:51:32 +01:00
assign->children[0]->str = wire_id;
Modified errors into warnings No longer false warnings for memories and assertions
2018-06-05 16:44:24 +02:00
assign->children[0]->was_checked = true;
Implemented part/bit select on memory read
2013-11-20 10:51:32 +01:00
if (current_block)
{
size_t assign_idx = 0;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
while (assign_idx < current_block->children.size() && current_block->children[assign_idx].get() != current_block_child)
Implemented part/bit select on memory read
2013-11-20 10:51:32 +01:00
assign_idx++;
log_assert(assign_idx < current_block->children.size());
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_block->children.insert(current_block->children.begin()+assign_idx, std::move(assign));
Implemented part/bit select on memory read
2013-11-20 10:51:32 +01:00
wire->is_reg = true;
}
else
{
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto proc = std::make_unique<AstNode>(location, AST_ALWAYS, std::make_unique<AstNode>(location, AST_BLOCK));
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
proc->children[0]->children.push_back(std::move(assign));
current_ast_mod->children.push_back(std::move(proc));
Implemented part/bit select on memory read
2013-11-20 10:51:32 +01:00
}
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = std::make_unique<AstNode>(location, AST_IDENTIFIER, children[1]->clone());
Implemented part/bit select on memory read
2013-11-20 10:51:32 +01:00
newNode->str = wire_id;
We can now handle array slices (e.g. $size(x[1]) etc. )
2020-09-16 23:55:17 +02:00
newNode->integer = integer; // save original number of dimensions for $size() etc.
Implemented part/bit select on memory read
2013-11-20 10:51:32 +01:00
newNode->id2ast = wire;
goto apply_newNode;
}
improved const function support
2014-06-06 22:55:02 +02:00
if (type == AST_WHILE)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("While loops are only allowed in constant functions!\n");
improved const function support
2014-06-06 22:55:02 +02:00
if (type == AST_REPEAT)
support repeat loops with constant repeat counts outside of constant functions
2019-04-09 18:28:32 +02:00
{
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto count = std::move(children[0]);
auto body = std::move(children[1]);
support repeat loops with constant repeat counts outside of constant functions
2019-04-09 18:28:32 +02:00
// eval count expression
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (count->simplify(true, stage, 32, true)) { }
support repeat loops with constant repeat counts outside of constant functions
2019-04-09 18:28:32 +02:00
if (count->type != AST_CONSTANT)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Repeat loops outside must have constant repeat counts!\n");
support repeat loops with constant repeat counts outside of constant functions
2019-04-09 18:28:32 +02:00
// convert to a block with the body repeated n times
type = AST_BLOCK;
children.clear();
for (int i = 0; i < count->bitsAsConst().as_int(); i++)
children.insert(children.begin(), body->clone());
did_something = true;
}
improved const function support
2014-06-06 22:55:02 +02:00
initial import
2013-01-05 11:13:26 +01:00
// unroll for loops and generate-for blocks
if ((type == AST_GENFOR || type == AST_FOR) && children.size() != 0)
{
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto& init_ast = children[0];
auto& while_ast = children[1];
auto& next_ast = children[2];
auto* body_ast = children[3].get();
initial import
2013-01-05 11:13:26 +01:00
Fixed generate-for (and disabled double warning for auto-wire)
2013-12-04 21:33:00 +01:00
while (body_ast->type == AST_GENBLOCK && body_ast->str.empty() &&
body_ast->children.size() == 1 && body_ast->children.at(0)->type == AST_GENBLOCK)
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
body_ast = body_ast->children.at(0).get();
Fixed generate-for (and disabled double warning for auto-wire)
2013-12-04 21:33:00 +01:00
Clearer for loop error messages
2020-07-25 18:35:03 +02:00
const char* loop_type_str = "procedural";
const char* var_type_str = "register";
AstNodeType var_type = AST_WIRE;
if (type == AST_GENFOR) {
loop_type_str = "generate";
var_type_str = "genvar";
var_type = AST_GENVAR;
}
initial import
2013-01-05 11:13:26 +01:00
if (init_ast->type != AST_ASSIGN_EQ)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Unsupported 1st expression of %s for-loop!\n", loop_type_str);
initial import
2013-01-05 11:13:26 +01:00
if (next_ast->type != AST_ASSIGN_EQ)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Unsupported 3rd expression of %s for-loop!\n", loop_type_str);
initial import
2013-01-05 11:13:26 +01:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
if (init_ast->children[0]->id2ast == nullptr || init_ast->children[0]->id2ast->type != var_type)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Left hand side of 1st expression of %s for-loop is not a %s!\n", loop_type_str, var_type_str);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
if (next_ast->children[0]->id2ast == nullptr || next_ast->children[0]->id2ast->type != var_type)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Left hand side of 3rd expression of %s for-loop is not a %s!\n", loop_type_str, var_type_str);
initial import
2013-01-05 11:13:26 +01:00
if (init_ast->children[0]->id2ast != next_ast->children[0]->id2ast)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Incompatible left-hand sides in 1st and 3rd expression of %s for-loop!\n", loop_type_str);
initial import
2013-01-05 11:13:26 +01:00
// eval 1st expression
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto varbuf = init_ast->children[1]->clone();
Determine correct signedness and expression width in for loop unrolling, fixes #370 Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-22 18:19:02 +02:00
{
int expr_width_hint = -1;
bool expr_sign_hint = true;
varbuf->detectSignWidth(expr_width_hint, expr_sign_hint);
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (varbuf->simplify(true, stage, 32, true)) { }
Determine correct signedness and expression width in for loop unrolling, fixes #370 Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-22 18:19:02 +02:00
}
initial import
2013-01-05 11:13:26 +01:00
if (varbuf->type != AST_CONSTANT)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Right hand side of 1st expression of %s for-loop is not constant!\n", loop_type_str);
initial import
2013-01-05 11:13:26 +01:00
Preserve size of $genval$-s in for loops
2019-12-12 01:26:26 +01:00
auto resolved = current_scope.at(init_ast->children[0]->str);
if (resolved->range_valid) {
verilog: instead of modifying localparam size, extend init constant expr
2020-02-06 02:19:42 +01:00
int const_size = varbuf->range_left - varbuf->range_right;
int resolved_size = resolved->range_left - resolved->range_right;
if (const_size < resolved_size) {
for (int i = const_size; i < resolved_size; i++)
varbuf->bits.push_back(resolved->is_signed ? varbuf->bits.back() : State::S0);
varbuf->range_left = resolved->range_left;
varbuf->range_right = resolved->range_right;
varbuf->range_swapped = resolved->range_swapped;
varbuf->range_valid = resolved->range_valid;
}
Preserve size of $genval$-s in for loops
2019-12-12 01:26:26 +01:00
}
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
varbuf = std::make_unique<AstNode>(location, AST_LOCALPARAM, std::move(varbuf));
verilog: instead of modifying localparam size, extend init constant expr
2020-02-06 02:19:42 +01:00
varbuf->str = init_ast->children[0]->str;
initial import
2013-01-05 11:13:26 +01:00
AstNode *backup_scope_varbuf = current_scope[varbuf->str];
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_scope[varbuf->str] = varbuf.get();
initial import
2013-01-05 11:13:26 +01:00
size_t current_block_idx = 0;
if (type == AST_FOR) {
while (current_block_idx < current_block->children.size() &&
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_block->children[current_block_idx].get() != current_block_child)
initial import
2013-01-05 11:13:26 +01:00
current_block_idx++;
}
while (1)
{
// eval 2nd expression
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto buf = while_ast->clone();
Determine correct signedness and expression width in for loop unrolling, fixes #370 Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-22 18:19:02 +02:00
{
int expr_width_hint = -1;
bool expr_sign_hint = true;
buf->detectSignWidth(expr_width_hint, expr_sign_hint);
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (buf->simplify(true, stage, expr_width_hint, expr_sign_hint)) { }
Determine correct signedness and expression width in for loop unrolling, fixes #370 Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-22 18:19:02 +02:00
}
initial import
2013-01-05 11:13:26 +01:00
if (buf->type != AST_CONSTANT)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("2nd expression of %s for-loop is not constant!\n", loop_type_str);
initial import
2013-01-05 11:13:26 +01:00
if (buf->integer == 0) {
break;
}
// expand body
int index = varbuf->children[0]->integer;
verilog: significant block scoping improvements This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
2021-01-27 19:30:22 +01:00
log_assert(body_ast->type == AST_GENBLOCK || body_ast->type == AST_BLOCK);
log_assert(!body_ast->str.empty());
buf = body_ast->clone();
initial import
2013-01-05 11:13:26 +01:00
std::stringstream sstr;
sstr << buf->str << "[" << index << "].";
verilog: significant block scoping improvements This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
2021-01-27 19:30:22 +01:00
std::string prefix = sstr.str();
// create a scoped localparam for the current value of the loop variable
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto local_index = varbuf->clone();
verilog: significant block scoping improvements This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
2021-01-27 19:30:22 +01:00
size_t pos = local_index->str.rfind('.');
if (pos != std::string::npos) // remove outer prefix
local_index->str = "\\" + local_index->str.substr(pos + 1);
local_index->str = prefix_id(prefix, local_index->str);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_scope[local_index->str] = local_index.get();
current_ast_mod->children.push_back(std::move(local_index));
verilog: significant block scoping improvements This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
2021-01-27 19:30:22 +01:00
buf->expand_genblock(prefix);
initial import
2013-01-05 11:13:26 +01:00
if (type == AST_GENFOR) {
Another name resolution bugfix for generate blocks
2013-11-20 13:57:40 +01:00
for (size_t i = 0; i < buf->children.size(); i++) {
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
buf->children[i]->simplify(const_fold, stage, -1, false);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_ast_mod->children.push_back(std::move(buf->children[i]));
Another name resolution bugfix for generate blocks
2013-11-20 13:57:40 +01:00
}
initial import
2013-01-05 11:13:26 +01:00
} else {
for (size_t i = 0; i < buf->children.size(); i++)
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_block->children.insert(current_block->children.begin() + current_block_idx++, std::move(buf->children[i]));
initial import
2013-01-05 11:13:26 +01:00
}
buf->children.clear();
// eval 3rd expression
buf = next_ast->children[1]->clone();
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
buf->set_in_param_flag(true);
Determine correct signedness and expression width in for loop unrolling, fixes #370 Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-22 18:19:02 +02:00
{
int expr_width_hint = -1;
bool expr_sign_hint = true;
buf->detectSignWidth(expr_width_hint, expr_sign_hint);
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (buf->simplify(true, stage, expr_width_hint, expr_sign_hint)) { }
Determine correct signedness and expression width in for loop unrolling, fixes #370 Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-22 18:19:02 +02:00
}
initial import
2013-01-05 11:13:26 +01:00
if (buf->type != AST_CONSTANT)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Right hand side of 3rd expression of %s for-loop is not constant (%s)!\n", loop_type_str, type2str(buf->type).c_str());
initial import
2013-01-05 11:13:26 +01:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
varbuf->children[0] = std::move(buf);
initial import
2013-01-05 11:13:26 +01:00
}
Add final loop variable assignment when unrolling for-loops, fixes #968 Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 15:03:32 +02:00
if (type == AST_FOR) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto buf = next_ast->clone();
Add final loop variable assignment when unrolling for-loops, fixes #968 Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 15:03:32 +02:00
buf->children[1] = varbuf->children[0]->clone();
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_block->children.insert(current_block->children.begin() + current_block_idx++, std::move(buf));
Add final loop variable assignment when unrolling for-loops, fixes #968 Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 15:03:32 +02:00
}
initial import
2013-01-05 11:13:26 +01:00
current_scope[varbuf->str] = backup_scope_varbuf;
delete_children();
did_something = true;
}
Added handling of local memories and error for local decls in unnamed blocks
2017-01-04 16:03:04 +01:00
// check for local objects in unnamed block
if (type == AST_BLOCK && str.empty())
{
for (size_t i = 0; i < children.size(); i++)
sv: Switch parser to glr, prep for typedef Signed-off-by: David Shah <dave@ds0.me>
2019-09-19 21:43:13 +02:00
if (children[i]->type == AST_WIRE || children[i]->type == AST_MEMORY || children[i]->type == AST_PARAMETER || children[i]->type == AST_LOCALPARAM || children[i]->type == AST_TYPEDEF)
verilog: significant block scoping improvements This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
2021-01-27 19:30:22 +01:00
{
neater errors, lost in the sauce of source
2025-06-18 18:05:48 +02:00
log_assert(!sv_mode_but_global_and_used_for_literally_one_condition);
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
children[i]->input_error("Local declaration in unnamed block is only supported in SystemVerilog mode!\n");
verilog: significant block scoping improvements This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
2021-01-27 19:30:22 +01:00
}
Added handling of local memories and error for local decls in unnamed blocks
2017-01-04 16:03:04 +01:00
}
Added support for local regs in named blocks
2013-12-04 09:10:16 +01:00
// transform block with name
if (type == AST_BLOCK && !str.empty())
{
verilog: significant block scoping improvements This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
2021-01-27 19:30:22 +01:00
expand_genblock(str + ".");
Added support for local regs in named blocks
2013-12-04 09:10:16 +01:00
sv: auto add nosync to certain always_comb local vars If a local variable is always assigned before it is used, then adding nosync prevents latches from being needlessly generated.
2022-01-07 06:04:00 +01:00
// if this is an autonamed block is in an always_comb
if (current_always && current_always->attributes.count(ID::always_comb)
sv: fix always_comb auto nosync for nested and function blocks
2022-02-22 16:57:08 +01:00
&& is_autonamed_block(str))
sv: auto add nosync to certain always_comb local vars If a local variable is always assigned before it is used, then adding nosync prevents latches from being needlessly generated.
2022-01-07 06:04:00 +01:00
// track local variables in this block so we can consider adding
// nosync once the block has been fully elaborated
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : children)
sv: auto add nosync to certain always_comb local vars If a local variable is always assigned before it is used, then adding nosync prevents latches from being needlessly generated.
2022-01-07 06:04:00 +01:00
if (child->type == AST_WIRE &&
!child->attributes.count(ID::nosync))
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
mark_auto_nosync(this, child.get());
sv: auto add nosync to certain always_comb local vars If a local variable is always assigned before it is used, then adding nosync prevents latches from being needlessly generated.
2022-01-07 06:04:00 +01:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
std::vector<std::unique_ptr<AstNode>> new_children;
Added support for local regs in named blocks
2013-12-04 09:10:16 +01:00
for (size_t i = 0; i < children.size(); i++)
sv: Switch parser to glr, prep for typedef Signed-off-by: David Shah <dave@ds0.me>
2019-09-19 21:43:13 +02:00
if (children[i]->type == AST_WIRE || children[i]->type == AST_MEMORY || children[i]->type == AST_PARAMETER || children[i]->type == AST_LOCALPARAM || children[i]->type == AST_TYPEDEF) {
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
children[i]->simplify(false, stage, -1, false);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_scope[children[i]->str] = children[i].get();
current_ast_mod->children.push_back(std::move(children[i]));
Added support for local regs in named blocks
2013-12-04 09:10:16 +01:00
} else
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
new_children.push_back(std::move(children[i]));
Added support for local regs in named blocks
2013-12-04 09:10:16 +01:00
children.swap(new_children);
did_something = true;
str.clear();
}
Fixed handling of unconditional generate blocks
2013-03-26 09:44:54 +01:00
// simplify unconditional generate block
if (type == AST_GENBLOCK && children.size() != 0)
{
if (!str.empty()) {
verilog: significant block scoping improvements This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
2021-01-27 19:30:22 +01:00
expand_genblock(str + ".");
Fixed handling of unconditional generate blocks
2013-03-26 09:44:54 +01:00
}
Another name resolution bugfix for generate blocks
2013-11-20 13:57:40 +01:00
for (size_t i = 0; i < children.size(); i++) {
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
children[i]->simplify(const_fold, stage, -1, false);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_ast_mod->children.push_back(std::move(children[i]));
Another name resolution bugfix for generate blocks
2013-11-20 13:57:40 +01:00
}
Fixed handling of unconditional generate blocks
2013-03-26 09:44:54 +01:00
children.clear();
did_something = true;
}
initial import
2013-01-05 11:13:26 +01:00
// simplify generate-if blocks
if (type == AST_GENIF && children.size() != 0)
{
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto buf = children[0]->clone();
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (buf->simplify(true, stage, width_hint, sign_hint)) { }
initial import
2013-01-05 11:13:26 +01:00
if (buf->type != AST_CONSTANT) {
Fixed const folding in corner cases with parameters
2013-11-07 14:08:53 +01:00
// for (auto f : log_files)
// dumpAst(f, "verilog-ast> ");
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Condition for generate if is not constant!\n");
initial import
2013-01-05 11:13:26 +01:00
}
Various improvements in support for generate statements
2013-12-04 21:06:54 +01:00
if (buf->asBool() != 0) {
initial import
2013-01-05 11:13:26 +01:00
buf = children[1]->clone();
} else {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
buf = children.size() > 2 ? children[2]->clone() : nullptr;
initial import
2013-01-05 11:13:26 +01:00
}
if (buf)
{
if (buf->type != AST_GENBLOCK)
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
buf = std::make_unique<AstNode>(location, AST_GENBLOCK, std::move(buf));
initial import
2013-01-05 11:13:26 +01:00
if (!buf->str.empty()) {
verilog: significant block scoping improvements This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
2021-01-27 19:30:22 +01:00
buf->expand_genblock(buf->str + ".");
initial import
2013-01-05 11:13:26 +01:00
}
Another name resolution bugfix for generate blocks
2013-11-20 13:57:40 +01:00
for (size_t i = 0; i < buf->children.size(); i++) {
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
buf->children[i]->simplify(const_fold, stage, -1, false);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_ast_mod->children.push_back(std::move(buf->children[i]));
Another name resolution bugfix for generate blocks
2013-11-20 13:57:40 +01:00
}
initial import
2013-01-05 11:13:26 +01:00
buf->children.clear();
}
delete_children();
did_something = true;
}
Various improvements in support for generate statements
2013-12-04 21:06:54 +01:00
// simplify generate-case blocks
if (type == AST_GENCASE && children.size() != 0)
{
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto buf = children[0]->clone();
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (buf->simplify(true, stage, width_hint, sign_hint)) { }
Various improvements in support for generate statements
2013-12-04 21:06:54 +01:00
if (buf->type != AST_CONSTANT) {
// for (auto f : log_files)
// dumpAst(f, "verilog-ast> ");
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Condition for generate case is not constant!\n");
Various improvements in support for generate statements
2013-12-04 21:06:54 +01:00
}
bool ref_signed = buf->is_signed;
RTLIL::Const ref_value = buf->bitsAsConst();
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
AstNode *selected_case = nullptr;
Various improvements in support for generate statements
2013-12-04 21:06:54 +01:00
for (size_t i = 1; i < children.size(); i++)
{
Fixed handling of parameters and const functions in casex/casez pattern
2016-04-21 15:31:54 +02:00
log_assert(children.at(i)->type == AST_COND || children.at(i)->type == AST_CONDX || children.at(i)->type == AST_CONDZ);
Various improvements in support for generate statements
2013-12-04 21:06:54 +01:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
AstNode *this_genblock = nullptr;
for (auto& child : children.at(i)->children) {
log_assert(this_genblock == nullptr);
Various improvements in support for generate statements
2013-12-04 21:06:54 +01:00
if (child->type == AST_GENBLOCK)
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
this_genblock = child.get();
Various improvements in support for generate statements
2013-12-04 21:06:54 +01:00
}
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : children.at(i)->children)
Various improvements in support for generate statements
2013-12-04 21:06:54 +01:00
{
if (child->type == AST_DEFAULT) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
if (selected_case == nullptr)
Various improvements in support for generate statements
2013-12-04 21:06:54 +01:00
selected_case = this_genblock;
continue;
}
if (child->type == AST_GENBLOCK)
continue;
buf = child->clone();
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
buf->set_in_param_flag(true);
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (buf->simplify(true, stage, width_hint, sign_hint)) { }
Various improvements in support for generate statements
2013-12-04 21:06:54 +01:00
if (buf->type != AST_CONSTANT) {
// for (auto f : log_files)
// dumpAst(f, "verilog-ast> ");
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Expression in generate case is not constant!\n");
Various improvements in support for generate statements
2013-12-04 21:06:54 +01:00
}
Fixed two memory leaks in ast simplify
2014-07-25 13:07:31 +02:00
bool is_selected = RTLIL::const_eq(ref_value, buf->bitsAsConst(), ref_signed && buf->is_signed, ref_signed && buf->is_signed, 1).as_bool();
if (is_selected) {
Various improvements in support for generate statements
2013-12-04 21:06:54 +01:00
selected_case = this_genblock;
i = children.size();
break;
}
}
}
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
if (selected_case != nullptr)
Various improvements in support for generate statements
2013-12-04 21:06:54 +01:00
{
log_assert(selected_case->type == AST_GENBLOCK);
buf = selected_case->clone();
if (!buf->str.empty()) {
verilog: significant block scoping improvements This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
2021-01-27 19:30:22 +01:00
buf->expand_genblock(buf->str + ".");
Various improvements in support for generate statements
2013-12-04 21:06:54 +01:00
}
for (size_t i = 0; i < buf->children.size(); i++) {
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
buf->children[i]->simplify(const_fold, stage, -1, false);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_ast_mod->children.push_back(std::move(buf->children[i]));
Various improvements in support for generate statements
2013-12-04 21:06:54 +01:00
}
buf->children.clear();
}
delete_children();
did_something = true;
}
Add support for cell arrays
2014-06-07 11:48:50 +02:00
// unroll cell arrays
if (type == AST_CELLARRAY)
{
if (!children.at(0)->range_valid)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Non-constant array range on cell array.\n");
Add support for cell arrays
2014-06-07 11:48:50 +02:00
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = std::make_unique<AstNode>(location, AST_GENBLOCK);
Import more std:: stuff into Yosys namespace
2015-10-25 19:30:49 +01:00
int num = max(children.at(0)->range_left, children.at(0)->range_right) - min(children.at(0)->range_left, children.at(0)->range_right) + 1;
Add support for cell arrays
2014-06-07 11:48:50 +02:00
for (int i = 0; i < num; i++) {
int idx = children.at(0)->range_left > children.at(0)->range_right ? children.at(0)->range_right + i : children.at(0)->range_right - i;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto new_cell_owned = children.at(1)->clone();
auto* new_cell = new_cell_owned.get();
newNode->children.push_back(std::move(new_cell_owned));
Add support for cell arrays
2014-06-07 11:48:50 +02:00
new_cell->str += stringf("[%d]", idx);
if (new_cell->type == AST_PRIMITIVE) {
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Cell arrays of primitives are currently not supported.\n");
Add support for cell arrays
2014-06-07 11:48:50 +02:00
} else {
simplify: Skip AST_PRIMITIVE in AST_CELLARRAY Otherwise the `AST_PRIMITIVE` simplifies to the corresponding function and is no longer caught by the check for `AST_PRIMITIVE`s, raising an assertion error instead of an input error. Add bug4785.ys to tests/verilog to demonstrate.
2025-03-25 00:15:54 +01:00
this->dumpAst(NULL, " ");
Add support for cell arrays
2014-06-07 11:48:50 +02:00
log_assert(new_cell->children.at(0)->type == AST_CELLTYPE);
new_cell->children.at(0)->str = stringf("$array:%d:%d:%s", i, num, new_cell->children.at(0)->str.c_str());
}
}
goto apply_newNode;
}
Spell check (by Larry Doolittle)
2015-08-14 10:56:05 +02:00
// replace primitives with assignments
initial import
2013-01-05 11:13:26 +01:00
if (type == AST_PRIMITIVE)
{
if (children.size() < 2)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Insufficient number of arguments for primitive `%s'!\n", str.c_str());
initial import
2013-01-05 11:13:26 +01:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
std::vector<std::unique_ptr<AstNode>> children_list;
for (auto& child : children) {
Using log_assert() instead of assert()
2014-07-28 11:08:55 +02:00
log_assert(child->type == AST_ARGUMENT);
log_assert(child->children.size() == 1);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
children_list.push_back(std::move(child->children[0]));
initial import
2013-01-05 11:13:26 +01:00
child->children.clear();
}
children.clear();
Added support for notif0/notif1 primitives
2013-08-20 11:23:59 +02:00
if (str == "bufif0" || str == "bufif1" || str == "notif0" || str == "notif1")
Added support for bufif0/bufif1 primitives
2013-08-19 19:50:04 +02:00
{
if (children_list.size() != 3)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Invalid number of arguments for primitive `%s'!\n", str.c_str());
initial import
2013-01-05 11:13:26 +01:00
Added support for bufif0/bufif1 primitives
2013-08-19 19:50:04 +02:00
std::vector<RTLIL::State> z_const(1, RTLIL::State::Sz);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto& mux_input = children_list.at(1);
Added support for notif0/notif1 primitives
2013-08-20 11:23:59 +02:00
if (str == "notif0" || str == "notif1") {
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
mux_input = std::make_unique<AstNode>(location, AST_BIT_NOT, std::move(mux_input));
Added support for notif0/notif1 primitives
2013-08-20 11:23:59 +02:00
}
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto node = std::make_unique<AstNode>(location, AST_TERNARY, std::move(children_list.at(2)));
Added support for bufif0/bufif1 primitives
2013-08-19 19:50:04 +02:00
if (str == "bufif0") {
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
node->children.push_back(AstNode::mkconst_bits(location, z_const, false));
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
node->children.push_back(std::move(mux_input));
Added support for bufif0/bufif1 primitives
2013-08-19 19:50:04 +02:00
} else {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
node->children.push_back(std::move(mux_input));
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
node->children.push_back(AstNode::mkconst_bits(location, z_const, false));
Added support for bufif0/bufif1 primitives
2013-08-19 19:50:04 +02:00
}
str.clear();
type = AST_ASSIGN;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
children.push_back(std::move(children_list.at(0)));
Fixed remaining cases where we check fo wire reg/wire incorrect assignments on Yosys-generated assignments. In this case, offending code was: module top(input in, output out); function func; input arg; func = arg; endfunction assign out = func(in); endmodule
2018-09-18 00:23:40 +02:00
children.back()->was_checked = true;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
children.push_back(std::move(node));
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
fixup_hierarchy_flags();
Added support for bufif0/bufif1 primitives
2013-08-19 19:50:04 +02:00
did_something = true;
}
verilog: fix buf/not primitives with multiple outputs From IEEE1364-2005, section 7.3 buf and not gates: > These two logic gates shall have one input and one or more outputs. > The last terminal in the terminal list shall connect to the input of the > logic gate, and the other terminals shall connect to the outputs of > the logic gate. yosys does not follow this and instead interprets the first argument as the output, the second as the input and ignores the rest.
2021-03-17 00:18:36 +01:00
else if (str == "buf" || str == "not")
{
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto& input = children_list.back();
verilog: fix buf/not primitives with multiple outputs From IEEE1364-2005, section 7.3 buf and not gates: > These two logic gates shall have one input and one or more outputs. > The last terminal in the terminal list shall connect to the input of the > logic gate, and the other terminals shall connect to the outputs of > the logic gate. yosys does not follow this and instead interprets the first argument as the output, the second as the input and ignores the rest.
2021-03-17 00:18:36 +01:00
if (str == "not")
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
input = std::make_unique<AstNode>(location, AST_BIT_NOT, std::move(input));
verilog: fix buf/not primitives with multiple outputs From IEEE1364-2005, section 7.3 buf and not gates: > These two logic gates shall have one input and one or more outputs. > The last terminal in the terminal list shall connect to the input of the > logic gate, and the other terminals shall connect to the outputs of > the logic gate. yosys does not follow this and instead interprets the first argument as the output, the second as the input and ignores the rest.
2021-03-17 00:18:36 +01:00
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = std::make_unique<AstNode>(location, AST_GENBLOCK);
verilog: fix buf/not primitives with multiple outputs From IEEE1364-2005, section 7.3 buf and not gates: > These two logic gates shall have one input and one or more outputs. > The last terminal in the terminal list shall connect to the input of the > logic gate, and the other terminals shall connect to the outputs of > the logic gate. yosys does not follow this and instead interprets the first argument as the output, the second as the input and ignores the rest.
2021-03-17 00:18:36 +01:00
for (auto it = children_list.begin(); it != std::prev(children_list.end()); it++) {
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode->children.push_back(std::make_unique<AstNode>(location, AST_ASSIGN, std::move(*it), input->clone()));
verilog: fix buf/not primitives with multiple outputs From IEEE1364-2005, section 7.3 buf and not gates: > These two logic gates shall have one input and one or more outputs. > The last terminal in the terminal list shall connect to the input of the > logic gate, and the other terminals shall connect to the outputs of > the logic gate. yosys does not follow this and instead interprets the first argument as the output, the second as the input and ignores the rest.
2021-03-17 00:18:36 +01:00
newNode->children.back()->was_checked = true;
}
did_something = true;
}
Added support for bufif0/bufif1 primitives
2013-08-19 19:50:04 +02:00
else
{
AstNodeType op_type = AST_NONE;
bool invert_results = false;
if (str == "and")
op_type = AST_BIT_AND;
if (str == "nand")
op_type = AST_BIT_AND, invert_results = true;
if (str == "or")
op_type = AST_BIT_OR;
if (str == "nor")
op_type = AST_BIT_OR, invert_results = true;
if (str == "xor")
op_type = AST_BIT_XOR;
if (str == "xnor")
op_type = AST_BIT_XOR, invert_results = true;
Using log_assert() instead of assert()
2014-07-28 11:08:55 +02:00
log_assert(op_type != AST_NONE);
Added support for bufif0/bufif1 primitives
2013-08-19 19:50:04 +02:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto& node = children_list[1];
Added support for bufif0/bufif1 primitives
2013-08-19 19:50:04 +02:00
if (op_type != AST_POS)
verilog: set src attribute for primitives
2020-05-04 19:22:05 +02:00
for (size_t i = 2; i < children_list.size(); i++) {
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
node = std::make_unique<AstNode>(location, op_type, std::move(node), std::move(children_list[i]));
verilog: set src attribute for primitives
2020-05-04 19:22:05 +02:00
node->location = location;
}
Added support for bufif0/bufif1 primitives
2013-08-19 19:50:04 +02:00
if (invert_results)
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
node = std::make_unique<AstNode>(location, AST_BIT_NOT, std::move(node));
Added support for bufif0/bufif1 primitives
2013-08-19 19:50:04 +02:00
str.clear();
type = AST_ASSIGN;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
children.push_back(std::move(children_list[0]));
Fixed remaining cases where we check fo wire reg/wire incorrect assignments on Yosys-generated assignments. In this case, offending code was: module top(input in, output out); function func; input arg; func = arg; endfunction assign out = func(in); endmodule
2018-09-18 00:23:40 +02:00
children.back()->was_checked = true;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
children.push_back(std::move(node));
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
fixup_hierarchy_flags();
Added support for bufif0/bufif1 primitives
2013-08-19 19:50:04 +02:00
did_something = true;
}
initial import
2013-01-05 11:13:26 +01:00
}
// replace dynamic ranges in left-hand side expressions (e.g. "foo[bar] <= 1'b1;") with
Improved rewrite code for writing to bit slice (disabled for now) This adds the new rewrite rule. But it's still missing a check that makes sure the new rewrite rule is actually a valid substitute in the always block being processed. Therefore the new rewrite rule is just disabled for now. Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-01 12:43:42 +02:00
// either a big case block that selects the correct single-bit assignment, or mask and
// shift operations.
if (type == AST_ASSIGN_EQ || type == AST_ASSIGN_LE)
{
initial import
2013-01-05 11:13:26 +01:00
if (children[0]->type != AST_IDENTIFIER || children[0]->children.size() == 0)
goto skip_dynamic_range_lvalue_expansion;
if (children[0]->children[0]->range_valid || did_something)
goto skip_dynamic_range_lvalue_expansion;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
if (children[0]->id2ast == nullptr || children[0]->id2ast->type != AST_WIRE)
initial import
2013-01-05 11:13:26 +01:00
goto skip_dynamic_range_lvalue_expansion;
if (!children[0]->id2ast->range_valid)
goto skip_dynamic_range_lvalue_expansion;
Improved rewrite code for writing to bit slice (disabled for now) This adds the new rewrite rule. But it's still missing a check that makes sure the new rewrite rule is actually a valid substitute in the always block being processed. Therefore the new rewrite rule is just disabled for now. Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-01 12:43:42 +02:00
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
AST::AstNode *member_node = children[0]->get_struct_member();
Correction and optimization of nowrshmsk This makes tests/verilog/dynamic_range_lhs.v pass, after ensuring that nowrshmsk is actually tested. Stride is extracted from indexing of two-dimensional packed arrays and variable slices on the form dst[i*stride +: width] = src, and is used to optimize the generated CASE block. Also uses less confusing variable names for indexing of lhs wires.
2023-08-04 23:45:47 +02:00
int wire_width = member_node ?
member_node->range_left - member_node->range_right + 1 :
children[0]->id2ast->range_left - children[0]->id2ast->range_right + 1;
int wire_offset = children[0]->id2ast->range_right;
int result_width = 1;
Improved rewrite code for writing to bit slice (disabled for now) This adds the new rewrite rule. But it's still missing a check that makes sure the new rewrite rule is actually a valid substitute in the always block being processed. Therefore the new rewrite rule is just disabled for now. Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-01 12:43:42 +02:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
std::unique_ptr<AstNode> shift_expr = nullptr;
auto& range = children[0]->children[0];
Improved rewrite code for writing to bit slice (disabled for now) This adds the new rewrite rule. But it's still missing a check that makes sure the new rewrite rule is actually a valid substitute in the always block being processed. Therefore the new rewrite rule is just disabled for now. Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-01 12:43:42 +02:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
if (!try_determine_range_width(range.get(), result_width))
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
ast/simplify: Factor out helper to determine range width
2023-04-04 11:34:17 +02:00
if (range->children.size() >= 2)
initial import
2013-01-05 11:13:26 +01:00
shift_expr = range->children[1]->clone();
ast/simplify: Factor out helper to determine range width
2023-04-04 11:34:17 +02:00
else
shift_expr = range->children[0]->clone();
Improved rewrite code for writing to bit slice (disabled for now) This adds the new rewrite rule. But it's still missing a check that makes sure the new rewrite rule is actually a valid substitute in the always block being processed. Therefore the new rewrite rule is just disabled for now. Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-01 12:43:42 +02:00
Correction and optimization of nowrshmsk This makes tests/verilog/dynamic_range_lhs.v pass, after ensuring that nowrshmsk is actually tested. Stride is extracted from indexing of two-dimensional packed arrays and variable slices on the form dst[i*stride +: width] = src, and is used to optimize the generated CASE block. Also uses less confusing variable names for indexing of lhs wires.
2023-08-04 23:45:47 +02:00
bool use_case_method = children[0]->id2ast->get_bool_attribute(ID::nowrshmsk);
Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset, fixes #1990 Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-27 17:04:47 +02:00
Add latch detection for use_case_method in part-select write, fixes #2040 Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-06-04 23:10:03 +02:00
if (!use_case_method && current_always->detect_latch(children[0]->str))
use_case_method = true;
Correction and optimization of nowrshmsk This makes tests/verilog/dynamic_range_lhs.v pass, after ensuring that nowrshmsk is actually tested. Stride is extracted from indexing of two-dimensional packed arrays and variable slices on the form dst[i*stride +: width] = src, and is used to optimize the generated CASE block. Also uses less confusing variable names for indexing of lhs wires.
2023-08-04 23:45:47 +02:00
if (use_case_method) {
Improved rewrite code for writing to bit slice (disabled for now) This adds the new rewrite rule. But it's still missing a check that makes sure the new rewrite rule is actually a valid substitute in the always block being processed. Therefore the new rewrite rule is just disabled for now. Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-01 12:43:42 +02:00
// big case block
Correction and optimization of nowrshmsk This makes tests/verilog/dynamic_range_lhs.v pass, after ensuring that nowrshmsk is actually tested. Stride is extracted from indexing of two-dimensional packed arrays and variable slices on the form dst[i*stride +: width] = src, and is used to optimize the generated CASE block. Also uses less confusing variable names for indexing of lhs wires.
2023-08-04 23:45:47 +02:00
int stride = 1;
long long bitno_div = stride;
int case_width_hint;
bool case_sign_hint;
shift_expr->detectSignWidth(case_width_hint, case_sign_hint);
int max_width = case_width_hint;
if (member_node) { // Member in packed struct/union
// Clamp chunk to range of member within struct/union.
log_assert(!wire_offset && !children[0]->id2ast->range_swapped);
// When the (* nowrshmsk *) attribute is set, a CASE block is generated below
// to select the indexed bit slice. When a multirange array is indexed, the
// start of each possible slice is separated by the bit stride of the last
// index dimension, and we can optimize the CASE block accordingly.
// The dimension of the original array expression is saved in the 'integer' field.
int dims = children[0]->integer;
stride = wire_width;
for (int dim = 0; dim < dims; dim++) {
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
stride /= member_node->dimensions[dim].range_width;
Correction and optimization of nowrshmsk This makes tests/verilog/dynamic_range_lhs.v pass, after ensuring that nowrshmsk is actually tested. Stride is extracted from indexing of two-dimensional packed arrays and variable slices on the form dst[i*stride +: width] = src, and is used to optimize the generated CASE block. Also uses less confusing variable names for indexing of lhs wires.
2023-08-04 23:45:47 +02:00
}
bitno_div = stride;
} else {
// Extract (index)*(width) from non_opt_range pattern ((@selfsz@((index)*(width)))+(0)).
AstNode *lsb_expr =
shift_expr->type == AST_ADD && shift_expr->children[0]->type == AST_SELFSZ &&
shift_expr->children[1]->type == AST_CONSTANT && shift_expr->children[1]->integer == 0 ?
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
shift_expr->children[0]->children[0].get() :
shift_expr.get();
Correction and optimization of nowrshmsk This makes tests/verilog/dynamic_range_lhs.v pass, after ensuring that nowrshmsk is actually tested. Stride is extracted from indexing of two-dimensional packed arrays and variable slices on the form dst[i*stride +: width] = src, and is used to optimize the generated CASE block. Also uses less confusing variable names for indexing of lhs wires.
2023-08-04 23:45:47 +02:00
// Extract stride from indexing of two-dimensional packed arrays and
// variable slices on the form dst[i*stride +: width] = src.
if (lsb_expr->type == AST_MUL &&
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
(lsb_expr->children[0]->type == AST_CONSTANT ||
lsb_expr->children[1]->type == AST_CONSTANT))
Correction and optimization of nowrshmsk This makes tests/verilog/dynamic_range_lhs.v pass, after ensuring that nowrshmsk is actually tested. Stride is extracted from indexing of two-dimensional packed arrays and variable slices on the form dst[i*stride +: width] = src, and is used to optimize the generated CASE block. Also uses less confusing variable names for indexing of lhs wires.
2023-08-04 23:45:47 +02:00
{
int stride_ix = lsb_expr->children[1]->type == AST_CONSTANT;
stride = (int)lsb_expr->children[stride_ix]->integer;
bitno_div = stride != 0 ? stride : 1;
// Check whether i*stride can overflow.
int i_width;
bool i_sign;
lsb_expr->children[1 - stride_ix]->detectSignWidth(i_width, i_sign);
int stride_width;
bool stride_sign;
lsb_expr->children[stride_ix]->detectSignWidth(stride_width, stride_sign);
max_width = std::max(i_width, stride_width);
// Stride width calculated from actual stride value.
nowrshmsk: Check for stride==0 log2(0) returns -inf, which gives undefined behaviour when casting to an int. So catch the case when it's 0 just set the width to 0.
2025-01-31 00:15:53 +01:00
if (stride == 0)
stride_width = 0;
else
stride_width = std::ceil(std::log2(std::abs(stride)));
Correction and optimization of nowrshmsk This makes tests/verilog/dynamic_range_lhs.v pass, after ensuring that nowrshmsk is actually tested. Stride is extracted from indexing of two-dimensional packed arrays and variable slices on the form dst[i*stride +: width] = src, and is used to optimize the generated CASE block. Also uses less confusing variable names for indexing of lhs wires.
2023-08-04 23:45:47 +02:00
if (i_width + stride_width > max_width) {
// For (truncated) i*stride to be within the range of dst, the following must hold:
// i*stride ≡ bitno (mod shift_mod), i.e.
// i*stride = k*shift_mod + bitno
//
// The Diophantine equation on the form ax + by = c:
// stride*i - shift_mod*k = bitno
// has solutions iff c is a multiple of d = gcd(a, b), i.e.
// bitno mod gcd(stride, shift_mod) = 0
//
// long long is at least 64 bits in C++11
long long shift_mod = 1ll << (max_width - case_sign_hint);
simplify: std::gcd
2025-08-08 12:31:13 +02:00
bitno_div = std::gcd((long long)stride, shift_mod);
Correction and optimization of nowrshmsk This makes tests/verilog/dynamic_range_lhs.v pass, after ensuring that nowrshmsk is actually tested. Stride is extracted from indexing of two-dimensional packed arrays and variable slices on the form dst[i*stride +: width] = src, and is used to optimize the generated CASE block. Also uses less confusing variable names for indexing of lhs wires.
2023-08-04 23:45:47 +02:00
}
}
}
// long long is at least 64 bits in C++11
long long max_offset = (1ll << (max_width - case_sign_hint)) - 1;
long long min_offset = case_sign_hint ? -(1ll << (max_width - 1)) : 0;
Assign from rvalue via temporary register in nowrshmsk CASE Avoid repeating complex rvalue expressions for each condition.
2023-12-08 20:47:43 +01:00
// A temporary register holds the result of the (possibly complex) rvalue expression,
// avoiding repetition in each AST_COND below.
int rvalue_width;
bool rvalue_sign;
children[1]->detectSignWidth(rvalue_width, rvalue_sign);
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto rvalue = mktemp_logic(location, "$bitselwrite$rvalue$", current_ast_mod, true, rvalue_width - 1, 0, rvalue_sign);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto* rvalue_leaky = rvalue.get();
log("make 1\n");
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto case_node_owned = std::make_unique<AstNode>(location, AST_CASE, std::move(shift_expr));
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto* case_node = case_node_owned.get();
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = std::make_unique<AstNode>(location, AST_BLOCK,
std::make_unique<AstNode>(location, AST_ASSIGN_EQ, std::move(rvalue), children[1]->clone()),
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
std::move(case_node_owned));
Assign from rvalue via temporary register in nowrshmsk CASE Avoid repeating complex rvalue expressions for each condition.
2023-12-08 20:47:43 +01:00
Improved rewrite code for writing to bit slice (disabled for now) This adds the new rewrite rule. But it's still missing a check that makes sure the new rewrite rule is actually a valid substitute in the always block being processed. Therefore the new rewrite rule is just disabled for now. Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-01 12:43:42 +02:00
did_something = true;
Correction and optimization of nowrshmsk This makes tests/verilog/dynamic_range_lhs.v pass, after ensuring that nowrshmsk is actually tested. Stride is extracted from indexing of two-dimensional packed arrays and variable slices on the form dst[i*stride +: width] = src, and is used to optimize the generated CASE block. Also uses less confusing variable names for indexing of lhs wires.
2023-08-04 23:45:47 +02:00
for (int i = 1 - result_width; i < wire_width; i++) {
// Out of range indexes are handled in genrtlil.cc
int start_bit = wire_offset + i;
int end_bit = start_bit + result_width - 1;
// Check whether the current index can be generated by shift_expr.
if (start_bit < min_offset || start_bit > max_offset)
continue;
if (start_bit%bitno_div != 0 || (stride == 0 && start_bit != 0))
continue;
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto cond = std::make_unique<AstNode>(location, AST_COND, mkconst_int(location, start_bit, case_sign_hint, max_width));
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto lvalue = children[0]->clone();
Improved rewrite code for writing to bit slice (disabled for now) This adds the new rewrite rule. But it's still missing a check that makes sure the new rewrite rule is actually a valid substitute in the always block being processed. Therefore the new rewrite rule is just disabled for now. Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-01 12:43:42 +02:00
lvalue->delete_children();
Index struct/union members within corresponding wire chunks This guards against access to bits outside of struct/union members via dynamic indexing.
2023-02-28 18:45:55 +01:00
if (member_node)
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
lvalue->set_attribute(ID::wiretype, member_node->clone());
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
lvalue->children.push_back(std::make_unique<AstNode>(location, AST_RANGE,
mkconst_int(location, end_bit, true), mkconst_int(location, start_bit, true)));
cond->children.push_back(std::make_unique<AstNode>(location, AST_BLOCK, std::make_unique<AstNode>(location, std::move(type), std::move(lvalue), rvalue_leaky->clone())));
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
case_node->children.push_back(std::move(cond));
Improved rewrite code for writing to bit slice (disabled for now) This adds the new rewrite rule. But it's still missing a check that makes sure the new rewrite rule is actually a valid substitute in the always block being processed. Therefore the new rewrite rule is just disabled for now. Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-01 12:43:42 +02:00
}
Correction and optimization of nowrshmsk This makes tests/verilog/dynamic_range_lhs.v pass, after ensuring that nowrshmsk is actually tested. Stride is extracted from indexing of two-dimensional packed arrays and variable slices on the form dst[i*stride +: width] = src, and is used to optimize the generated CASE block. Also uses less confusing variable names for indexing of lhs wires.
2023-08-04 23:45:47 +02:00
} else {
// mask and shift operations
Simplify and correct AST for array slice assignment Corrects sign extension of the right hand side, and hopefully makes the code simpler to understand. Fixes #4064
2023-12-12 13:37:34 +01:00
// dst = (dst & ~(width'1 << lsb)) | unsigned'(width'(src)) << lsb)
Improved rewrite code for writing to bit slice (disabled for now) This adds the new rewrite rule. But it's still missing a check that makes sure the new rewrite rule is actually a valid substitute in the always block being processed. Therefore the new rewrite rule is just disabled for now. Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-01 12:43:42 +02:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto lvalue = children[0]->clone();
initial import
2013-01-05 11:13:26 +01:00
lvalue->delete_children();
Index struct/union members within corresponding wire chunks This guards against access to bits outside of struct/union members via dynamic indexing.
2023-02-28 18:45:55 +01:00
if (member_node)
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
lvalue->set_attribute(ID::wiretype, member_node->clone());
Improved rewrite code for writing to bit slice (disabled for now) This adds the new rewrite rule. But it's still missing a check that makes sure the new rewrite rule is actually a valid substitute in the always block being processed. Therefore the new rewrite rule is just disabled for now. Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-01 12:43:42 +02:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto old_data = lvalue->clone();
Add LookaheadRewriter for proper bitselwrite support Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-15 20:36:40 +02:00
if (type == AST_ASSIGN_LE)
old_data->lookahead = true;
Simplify and correct AST for array slice assignment Corrects sign extension of the right hand side, and hopefully makes the code simpler to understand. Fixes #4064
2023-12-12 13:37:34 +01:00
int shift_width_hint;
bool shift_sign_hint;
shift_expr->detectSignWidth(shift_width_hint, shift_sign_hint);
Improved rewrite code for writing to bit slice (disabled for now) This adds the new rewrite rule. But it's still missing a check that makes sure the new rewrite rule is actually a valid substitute in the always block being processed. Therefore the new rewrite rule is just disabled for now. Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-01 12:43:42 +02:00
Simplify and correct AST for array slice assignment Corrects sign extension of the right hand side, and hopefully makes the code simpler to understand. Fixes #4064
2023-12-12 13:37:34 +01:00
// All operations are carried out in a new block.
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = std::make_unique<AstNode>(location, AST_BLOCK);
Simplify and correct AST for array slice assignment Corrects sign extension of the right hand side, and hopefully makes the code simpler to understand. Fixes #4064
2023-12-12 13:37:34 +01:00
// Temporary register holding the result of the bit- or part-select position expression.
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto pos = mktemp_logic(location, "$bitselwrite$pos$", current_ast_mod, true, shift_width_hint - 1, 0, shift_sign_hint);
Simplify and correct AST for array slice assignment Corrects sign extension of the right hand side, and hopefully makes the code simpler to understand. Fixes #4064
2023-12-12 13:37:34 +01:00
// Calculate lsb from position.
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto shift_val = pos->clone();
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode->children.push_back(std::make_unique<AstNode>(location, AST_ASSIGN_EQ, std::move(pos), std::move(shift_expr)));
Simplify and correct AST for array slice assignment Corrects sign extension of the right hand side, and hopefully makes the code simpler to understand. Fixes #4064
2023-12-12 13:37:34 +01:00
// If the expression is signed, we must add an extra bit for possible negation of the most negative number.
// If the expression is unsigned, we must add an extra bit for sign.
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
shift_val = std::make_unique<AstNode>(location, AST_CAST_SIZE, mkconst_int(location, shift_width_hint + 1, true), std::move(shift_val));
Simplify and correct AST for array slice assignment Corrects sign extension of the right hand side, and hopefully makes the code simpler to understand. Fixes #4064
2023-12-12 13:37:34 +01:00
if (!shift_sign_hint)
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
shift_val = std::make_unique<AstNode>(location, AST_TO_SIGNED, std::move(shift_val));
verilog: fix dynamic dynamic range asgn elab
2022-01-18 07:18:12 +01:00
// offset the shift amount by the lower bound of the dimension
Simplify and correct AST for array slice assignment Corrects sign extension of the right hand side, and hopefully makes the code simpler to understand. Fixes #4064
2023-12-12 13:37:34 +01:00
if (wire_offset != 0)
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
shift_val = std::make_unique<AstNode>(location, AST_SUB, std::move(shift_val), mkconst_int(location, wire_offset, true));
Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset, fixes #1990 Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-27 17:04:47 +02:00
verilog: fix dynamic dynamic range asgn elab
2022-01-18 07:18:12 +01:00
// reflect the shift amount if the dimension is swapped
if (children[0]->id2ast->range_swapped)
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
shift_val = std::make_unique<AstNode>(location, AST_SUB, mkconst_int(location, wire_width - result_width, true), std::move(shift_val));
verilog: fix dynamic dynamic range asgn elab
2022-01-18 07:18:12 +01:00
// AST_SHIFT uses negative amounts for shifting left
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
shift_val = std::make_unique<AstNode>(location, AST_NEG, std::move(shift_val));
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto also_shift_val = shift_val->clone();
Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset, fixes #1990 Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-27 17:04:47 +02:00
Simplify and correct AST for array slice assignment Corrects sign extension of the right hand side, and hopefully makes the code simpler to understand. Fixes #4064
2023-12-12 13:37:34 +01:00
// dst = (dst & ~(width'1 << lsb)) | unsigned'(width'(src)) << lsb)
did_something = true;
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto bitmask = mkconst_bits(location, std::vector<RTLIL::State>(result_width, State::S1), false);
Simplify and correct AST for array slice assignment Corrects sign extension of the right hand side, and hopefully makes the code simpler to understand. Fixes #4064
2023-12-12 13:37:34 +01:00
newNode->children.push_back(
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
std::make_unique<AstNode>(location, std::move(type),
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
std::move(lvalue),
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
std::make_unique<AstNode>(location, AST_BIT_OR,
std::make_unique<AstNode>(location, AST_BIT_AND,
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
std::move(old_data),
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
std::make_unique<AstNode>(location, AST_BIT_NOT,
std::make_unique<AstNode>(location, AST_SHIFT,
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
std::move(bitmask),
std::move(shift_val)))),
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
std::make_unique<AstNode>(location, AST_SHIFT,
std::make_unique<AstNode>(location, AST_TO_UNSIGNED,
std::make_unique<AstNode>(location, AST_CAST_SIZE,
mkconst_int(location, result_width, true),
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
children[1]->clone())),
std::move(also_shift_val)))));
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
newNode->fixup_hierarchy_flags(true);
initial import
2013-01-05 11:13:26 +01:00
}
Improved rewrite code for writing to bit slice (disabled for now) This adds the new rewrite rule. But it's still missing a check that makes sure the new rewrite rule is actually a valid substitute in the always block being processed. Therefore the new rewrite rule is just disabled for now. Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-01 12:43:42 +02:00
initial import
2013-01-05 11:13:26 +01:00
goto apply_newNode;
}
skip_dynamic_range_lvalue_expansion:;
// found right-hand side identifier for memory -> replace with memory read port
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
if (stage > 1 && type == AST_IDENTIFIER && id2ast != nullptr && id2ast->type == AST_MEMORY && !in_lvalue &&
Fixed handling of memory read without address
2015-08-22 14:46:42 +02:00
children.size() == 1 && children[0]->type == AST_RANGE && children[0]->children.size() == 1) {
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
if (integer < (unsigned)id2ast->unpacked_dimensions)
input_error("Insufficient number of array indices for %s.\n", log_id(str));
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = std::make_unique<AstNode>(location, AST_MEMRD, children[0]->children[0]->clone());
initial import
2013-01-05 11:13:26 +01:00
newNode->str = str;
further improved early width and sign detection in ast simplifier
2013-11-04 06:04:42 +01:00
newNode->id2ast = id2ast;
initial import
2013-01-05 11:13:26 +01:00
goto apply_newNode;
}
Fixed mem assignment in left-hand-side concatenation
2016-07-08 14:31:06 +02:00
// assignment with nontrivial member in left-hand concat expression -> split assignment
if ((type == AST_ASSIGN_EQ || type == AST_ASSIGN_LE) && children[0]->type == AST_CONCAT && width_hint > 0)
{
bool found_nontrivial_member = false;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : children[0]->children) {
if (child->type == AST_IDENTIFIER && child->id2ast != nullptr && child->id2ast->type == AST_MEMORY)
Fixed mem assignment in left-hand-side concatenation
2016-07-08 14:31:06 +02:00
found_nontrivial_member = true;
}
if (found_nontrivial_member)
{
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = std::make_unique<AstNode>(location, AST_BLOCK);
Fixed mem assignment in left-hand-side concatenation
2016-07-08 14:31:06 +02:00
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto wire_tmp_owned = std::make_unique<AstNode>(location, AST_WIRE, std::make_unique<AstNode>(location, AST_RANGE, mkconst_int(location, width_hint-1, true), mkconst_int(location, 0, true)));
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto wire_tmp = wire_tmp_owned.get();
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
wire_tmp->str = stringf("$splitcmplxassign$%s:%d$%d", RTLIL::encode_filename(*location.begin.filename).c_str(), location.begin.line, autoidx++);
Fixed mem assignment in left-hand-side concatenation
2016-07-08 14:31:06 +02:00
current_scope[wire_tmp->str] = wire_tmp;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_ast_mod->children.push_back(std::move(wire_tmp_owned));
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
wire_tmp->set_attribute(ID::nosync, AstNode::mkconst_int(location, 1, false));
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (wire_tmp->simplify(true, 1, -1, false)) { }
Add splitcmplxassign test case and silence splitcmplxassign warning Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-01 10:01:54 +02:00
wire_tmp->is_logic = true;
Fixed mem assignment in left-hand-side concatenation
2016-07-08 14:31:06 +02:00
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto wire_tmp_id_owned = std::make_unique<AstNode>(location, AST_IDENTIFIER);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto* wire_tmp_id = wire_tmp_id_owned.get();
Fixed mem assignment in left-hand-side concatenation
2016-07-08 14:31:06 +02:00
wire_tmp_id->str = wire_tmp->str;
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode->children.push_back(std::make_unique<AstNode>(location, AST_ASSIGN_EQ, std::move(wire_tmp_id_owned), children[1]->clone()));
Fixed remaining cases where we check fo wire reg/wire incorrect assignments on Yosys-generated assignments. In this case, offending code was: module top(input in, output out); function func; input arg; func = arg; endfunction assign out = func(in); endmodule
2018-09-18 00:23:40 +02:00
newNode->children.back()->was_checked = true;
Fixed mem assignment in left-hand-side concatenation
2016-07-08 14:31:06 +02:00
int cursor = 0;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : children[0]->children)
Fixed mem assignment in left-hand-side concatenation
2016-07-08 14:31:06 +02:00
{
int child_width_hint = -1;
bool child_sign_hint = true;
child->detectSignWidth(child_width_hint, child_sign_hint);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto rhs = wire_tmp_id->clone();
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
rhs->children.push_back(std::make_unique<AstNode>(location, AST_RANGE, AstNode::mkconst_int(location, cursor+child_width_hint-1, true), AstNode::mkconst_int(location, cursor, true)));
newNode->children.push_back(std::make_unique<AstNode>(location, type, child->clone(), std::move(rhs)));
Fixed mem assignment in left-hand-side concatenation
2016-07-08 14:31:06 +02:00
cursor += child_width_hint;
}
goto apply_newNode;
}
}
initial import
2013-01-05 11:13:26 +01:00
// assignment with memory in left-hand side expression -> replace with memory write port
if (stage > 1 && (type == AST_ASSIGN_EQ || type == AST_ASSIGN_LE) && children[0]->type == AST_IDENTIFIER &&
Added support for constant bit- or part-select for memory writes
2014-07-17 13:13:21 +02:00
children[0]->id2ast && children[0]->id2ast->type == AST_MEMORY && children[0]->id2ast->children.size() >= 2 &&
children[0]->id2ast->children[0]->range_valid && children[0]->id2ast->children[1]->range_valid &&
Added AST_MULTIRANGE (arrays with more than 1 dimension)
2014-08-06 15:43:46 +02:00
(children[0]->children.size() == 1 || children[0]->children.size() == 2) && children[0]->children[0]->type == AST_RANGE)
initial import
2013-01-05 11:13:26 +01:00
{
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
if (children[0]->integer < (unsigned)children[0]->id2ast->unpacked_dimensions)
input_error("Insufficient number of array indices for %s.\n", log_id(str));
initial import
2013-01-05 11:13:26 +01:00
std::stringstream sstr;
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
sstr << "$memwr$" << children[0]->str << "$" << RTLIL::encode_filename(*location.begin.filename) << ":" << location.begin.line << "$" << (autoidx++);
initial import
2013-01-05 11:13:26 +01:00
std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA", id_en = sstr.str() + "_EN";
int mem_width, mem_size, addr_bits;
Some fixes in handling of signed arrays
2016-11-01 23:17:43 +01:00
bool mem_signed = children[0]->id2ast->is_signed;
initial import
2013-01-05 11:13:26 +01:00
children[0]->id2ast->meminfo(mem_width, mem_size, addr_bits);
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = std::make_unique<AstNode>(location, AST_BLOCK);
auto defNode = std::make_unique<AstNode>(location, AST_BLOCK);
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT. Before this commit, every initial assignment to a memory generated two wires and four assigns in a process. For unknown reasons (I did not investigate), large amounts of assigns cause quadratic slowdown later in the AST frontend, in processAst/removeSignalFromCaseTree. As a consequence, common and reasonable Verilog code, such as: reg [`WIDTH:0] mem [0:`DEPTH]; integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0; took extremely long time to be processed; around 80 s for a 8-wide, 8192-deep memory. After this commit, initial assignments where address and/or data are constant (after `generate`) do not incur the cost of intermediate wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant. This results in speedups of orders of magnitude for common memory sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep memory, and only 5.8 s to process a 8-wide, 131072-deep one. As a bonus, this change also results in nontrivial speedups later in the synthesis pipeline, since pass sequencing issues meant that all of these intermediate wires were subject to transformations such as width reduction, even though they existed solely to be constant folded away in `memory_collect`.
2020-01-01 21:18:28 +01:00
Fixed bug with memories that do not have a down-to-zero data width
2016-08-22 14:27:46 +02:00
int data_range_left = children[0]->id2ast->children[0]->range_left;
int data_range_right = children[0]->id2ast->children[0]->range_right;
int mem_data_range_offset = std::min(data_range_left, data_range_right);
Optimize memory address port width in wreduce and memory_collect, not verilog front-end
2016-08-19 18:38:25 +02:00
int addr_width_hint = -1;
bool addr_sign_hint = true;
children[0]->children[0]->children[0]->detectSignWidthWorker(addr_width_hint, addr_sign_hint);
addr_bits = std::max(addr_bits, addr_width_hint);
changes in verilog frontend for new $mem/$memwr WR_EN interface
2014-07-16 12:23:47 +02:00
std::vector<RTLIL::State> x_bits_addr, x_bits_data, set_bits_en;
Fixed bug in generation of undefs for $memwr MUXes
2014-02-22 17:08:00 +01:00
for (int i = 0; i < addr_bits; i++)
x_bits_addr.push_back(RTLIL::State::Sx);
Fixed two bugs in mem2reg functionality in AST frontend
2013-11-18 19:55:12 +01:00
for (int i = 0; i < mem_width; i++)
Fixed bug in generation of undefs for $memwr MUXes
2014-02-22 17:08:00 +01:00
x_bits_data.push_back(RTLIL::State::Sx);
changes in verilog frontend for new $mem/$memwr WR_EN interface
2014-07-16 12:23:47 +02:00
for (int i = 0; i < mem_width; i++)
set_bits_en.push_back(RTLIL::State::S1);
initial import
2013-01-05 11:13:26 +01:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
std::unique_ptr<AstNode> node_addr = nullptr;
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT. Before this commit, every initial assignment to a memory generated two wires and four assigns in a process. For unknown reasons (I did not investigate), large amounts of assigns cause quadratic slowdown later in the AST frontend, in processAst/removeSignalFromCaseTree. As a consequence, common and reasonable Verilog code, such as: reg [`WIDTH:0] mem [0:`DEPTH]; integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0; took extremely long time to be processed; around 80 s for a 8-wide, 8192-deep memory. After this commit, initial assignments where address and/or data are constant (after `generate`) do not incur the cost of intermediate wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant. This results in speedups of orders of magnitude for common memory sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep memory, and only 5.8 s to process a 8-wide, 131072-deep one. As a bonus, this change also results in nontrivial speedups later in the synthesis pipeline, since pass sequencing issues meant that all of these intermediate wires were subject to transformations such as width reduction, even though they existed solely to be constant folded away in `memory_collect`.
2020-01-01 21:18:28 +01:00
if (children[0]->children[0]->children[0]->isConst()) {
node_addr = children[0]->children[0]->children[0]->clone();
} else {
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto wire_addr_owned = std::make_unique<AstNode>(location, AST_WIRE, std::make_unique<AstNode>(location, AST_RANGE, mkconst_int(location, addr_bits-1, true), mkconst_int(location, 0, true)));
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto* wire_addr = wire_addr_owned.get();
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT. Before this commit, every initial assignment to a memory generated two wires and four assigns in a process. For unknown reasons (I did not investigate), large amounts of assigns cause quadratic slowdown later in the AST frontend, in processAst/removeSignalFromCaseTree. As a consequence, common and reasonable Verilog code, such as: reg [`WIDTH:0] mem [0:`DEPTH]; integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0; took extremely long time to be processed; around 80 s for a 8-wide, 8192-deep memory. After this commit, initial assignments where address and/or data are constant (after `generate`) do not incur the cost of intermediate wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant. This results in speedups of orders of magnitude for common memory sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep memory, and only 5.8 s to process a 8-wide, 131072-deep one. As a bonus, this change also results in nontrivial speedups later in the synthesis pipeline, since pass sequencing issues meant that all of these intermediate wires were subject to transformations such as width reduction, even though they existed solely to be constant folded away in `memory_collect`.
2020-01-01 21:18:28 +01:00
wire_addr->str = id_addr;
wire_addr->was_checked = true;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_ast_mod->children.push_back(std::move(wire_addr_owned));
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT. Before this commit, every initial assignment to a memory generated two wires and four assigns in a process. For unknown reasons (I did not investigate), large amounts of assigns cause quadratic slowdown later in the AST frontend, in processAst/removeSignalFromCaseTree. As a consequence, common and reasonable Verilog code, such as: reg [`WIDTH:0] mem [0:`DEPTH]; integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0; took extremely long time to be processed; around 80 s for a 8-wide, 8192-deep memory. After this commit, initial assignments where address and/or data are constant (after `generate`) do not incur the cost of intermediate wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant. This results in speedups of orders of magnitude for common memory sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep memory, and only 5.8 s to process a 8-wide, 131072-deep one. As a bonus, this change also results in nontrivial speedups later in the synthesis pipeline, since pass sequencing issues meant that all of these intermediate wires were subject to transformations such as width reduction, even though they existed solely to be constant folded away in `memory_collect`.
2020-01-01 21:18:28 +01:00
current_scope[wire_addr->str] = wire_addr;
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (wire_addr->simplify(true, 1, -1, false)) { }
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT. Before this commit, every initial assignment to a memory generated two wires and four assigns in a process. For unknown reasons (I did not investigate), large amounts of assigns cause quadratic slowdown later in the AST frontend, in processAst/removeSignalFromCaseTree. As a consequence, common and reasonable Verilog code, such as: reg [`WIDTH:0] mem [0:`DEPTH]; integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0; took extremely long time to be processed; around 80 s for a 8-wide, 8192-deep memory. After this commit, initial assignments where address and/or data are constant (after `generate`) do not incur the cost of intermediate wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant. This results in speedups of orders of magnitude for common memory sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep memory, and only 5.8 s to process a 8-wide, 131072-deep one. As a bonus, this change also results in nontrivial speedups later in the synthesis pipeline, since pass sequencing issues meant that all of these intermediate wires were subject to transformations such as width reduction, even though they existed solely to be constant folded away in `memory_collect`.
2020-01-01 21:18:28 +01:00
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto assign_addr = std::make_unique<AstNode>(location, AST_ASSIGN_EQ, std::make_unique<AstNode>(location, AST_IDENTIFIER), mkconst_bits(location, x_bits_addr, false));
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT. Before this commit, every initial assignment to a memory generated two wires and four assigns in a process. For unknown reasons (I did not investigate), large amounts of assigns cause quadratic slowdown later in the AST frontend, in processAst/removeSignalFromCaseTree. As a consequence, common and reasonable Verilog code, such as: reg [`WIDTH:0] mem [0:`DEPTH]; integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0; took extremely long time to be processed; around 80 s for a 8-wide, 8192-deep memory. After this commit, initial assignments where address and/or data are constant (after `generate`) do not incur the cost of intermediate wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant. This results in speedups of orders of magnitude for common memory sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep memory, and only 5.8 s to process a 8-wide, 131072-deep one. As a bonus, this change also results in nontrivial speedups later in the synthesis pipeline, since pass sequencing issues meant that all of these intermediate wires were subject to transformations such as width reduction, even though they existed solely to be constant folded away in `memory_collect`.
2020-01-01 21:18:28 +01:00
assign_addr->children[0]->str = id_addr;
assign_addr->children[0]->was_checked = true;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
defNode->children.push_back(std::move(assign_addr));
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT. Before this commit, every initial assignment to a memory generated two wires and four assigns in a process. For unknown reasons (I did not investigate), large amounts of assigns cause quadratic slowdown later in the AST frontend, in processAst/removeSignalFromCaseTree. As a consequence, common and reasonable Verilog code, such as: reg [`WIDTH:0] mem [0:`DEPTH]; integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0; took extremely long time to be processed; around 80 s for a 8-wide, 8192-deep memory. After this commit, initial assignments where address and/or data are constant (after `generate`) do not incur the cost of intermediate wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant. This results in speedups of orders of magnitude for common memory sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep memory, and only 5.8 s to process a 8-wide, 131072-deep one. As a bonus, this change also results in nontrivial speedups later in the synthesis pipeline, since pass sequencing issues meant that all of these intermediate wires were subject to transformations such as width reduction, even though they existed solely to be constant folded away in `memory_collect`.
2020-01-01 21:18:28 +01:00
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
assign_addr = std::make_unique<AstNode>(location, AST_ASSIGN_EQ, std::make_unique<AstNode>(location, AST_IDENTIFIER), children[0]->children[0]->children[0]->clone());
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT. Before this commit, every initial assignment to a memory generated two wires and four assigns in a process. For unknown reasons (I did not investigate), large amounts of assigns cause quadratic slowdown later in the AST frontend, in processAst/removeSignalFromCaseTree. As a consequence, common and reasonable Verilog code, such as: reg [`WIDTH:0] mem [0:`DEPTH]; integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0; took extremely long time to be processed; around 80 s for a 8-wide, 8192-deep memory. After this commit, initial assignments where address and/or data are constant (after `generate`) do not incur the cost of intermediate wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant. This results in speedups of orders of magnitude for common memory sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep memory, and only 5.8 s to process a 8-wide, 131072-deep one. As a bonus, this change also results in nontrivial speedups later in the synthesis pipeline, since pass sequencing issues meant that all of these intermediate wires were subject to transformations such as width reduction, even though they existed solely to be constant folded away in `memory_collect`.
2020-01-01 21:18:28 +01:00
assign_addr->children[0]->str = id_addr;
assign_addr->children[0]->was_checked = true;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
newNode->children.push_back(std::move(assign_addr));
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT. Before this commit, every initial assignment to a memory generated two wires and four assigns in a process. For unknown reasons (I did not investigate), large amounts of assigns cause quadratic slowdown later in the AST frontend, in processAst/removeSignalFromCaseTree. As a consequence, common and reasonable Verilog code, such as: reg [`WIDTH:0] mem [0:`DEPTH]; integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0; took extremely long time to be processed; around 80 s for a 8-wide, 8192-deep memory. After this commit, initial assignments where address and/or data are constant (after `generate`) do not incur the cost of intermediate wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant. This results in speedups of orders of magnitude for common memory sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep memory, and only 5.8 s to process a 8-wide, 131072-deep one. As a bonus, this change also results in nontrivial speedups later in the synthesis pipeline, since pass sequencing issues meant that all of these intermediate wires were subject to transformations such as width reduction, even though they existed solely to be constant folded away in `memory_collect`.
2020-01-01 21:18:28 +01:00
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
node_addr = std::make_unique<AstNode>(location, AST_IDENTIFIER);
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT. Before this commit, every initial assignment to a memory generated two wires and four assigns in a process. For unknown reasons (I did not investigate), large amounts of assigns cause quadratic slowdown later in the AST frontend, in processAst/removeSignalFromCaseTree. As a consequence, common and reasonable Verilog code, such as: reg [`WIDTH:0] mem [0:`DEPTH]; integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0; took extremely long time to be processed; around 80 s for a 8-wide, 8192-deep memory. After this commit, initial assignments where address and/or data are constant (after `generate`) do not incur the cost of intermediate wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant. This results in speedups of orders of magnitude for common memory sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep memory, and only 5.8 s to process a 8-wide, 131072-deep one. As a bonus, this change also results in nontrivial speedups later in the synthesis pipeline, since pass sequencing issues meant that all of these intermediate wires were subject to transformations such as width reduction, even though they existed solely to be constant folded away in `memory_collect`.
2020-01-01 21:18:28 +01:00
node_addr->str = id_addr;
}
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
std::unique_ptr<AstNode> node_data = nullptr;
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT. Before this commit, every initial assignment to a memory generated two wires and four assigns in a process. For unknown reasons (I did not investigate), large amounts of assigns cause quadratic slowdown later in the AST frontend, in processAst/removeSignalFromCaseTree. As a consequence, common and reasonable Verilog code, such as: reg [`WIDTH:0] mem [0:`DEPTH]; integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0; took extremely long time to be processed; around 80 s for a 8-wide, 8192-deep memory. After this commit, initial assignments where address and/or data are constant (after `generate`) do not incur the cost of intermediate wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant. This results in speedups of orders of magnitude for common memory sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep memory, and only 5.8 s to process a 8-wide, 131072-deep one. As a bonus, this change also results in nontrivial speedups later in the synthesis pipeline, since pass sequencing issues meant that all of these intermediate wires were subject to transformations such as width reduction, even though they existed solely to be constant folded away in `memory_collect`.
2020-01-01 21:18:28 +01:00
if (children[0]->children.size() == 1 && children[1]->isConst()) {
node_data = children[1]->clone();
} else {
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto wire_data_owned = std::make_unique<AstNode>(location, AST_WIRE, std::make_unique<AstNode>(location, AST_RANGE, mkconst_int(location, mem_width-1, true), mkconst_int(location, 0, true)));
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto* wire_data = wire_data_owned.get();
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT. Before this commit, every initial assignment to a memory generated two wires and four assigns in a process. For unknown reasons (I did not investigate), large amounts of assigns cause quadratic slowdown later in the AST frontend, in processAst/removeSignalFromCaseTree. As a consequence, common and reasonable Verilog code, such as: reg [`WIDTH:0] mem [0:`DEPTH]; integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0; took extremely long time to be processed; around 80 s for a 8-wide, 8192-deep memory. After this commit, initial assignments where address and/or data are constant (after `generate`) do not incur the cost of intermediate wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant. This results in speedups of orders of magnitude for common memory sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep memory, and only 5.8 s to process a 8-wide, 131072-deep one. As a bonus, this change also results in nontrivial speedups later in the synthesis pipeline, since pass sequencing issues meant that all of these intermediate wires were subject to transformations such as width reduction, even though they existed solely to be constant folded away in `memory_collect`.
2020-01-01 21:18:28 +01:00
wire_data->str = id_data;
wire_data->was_checked = true;
wire_data->is_signed = mem_signed;
current_scope[wire_data->str] = wire_data;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_ast_mod->children.push_back(std::move(wire_data_owned));
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (wire_data->simplify(true, 1, -1, false)) { }
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT. Before this commit, every initial assignment to a memory generated two wires and four assigns in a process. For unknown reasons (I did not investigate), large amounts of assigns cause quadratic slowdown later in the AST frontend, in processAst/removeSignalFromCaseTree. As a consequence, common and reasonable Verilog code, such as: reg [`WIDTH:0] mem [0:`DEPTH]; integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0; took extremely long time to be processed; around 80 s for a 8-wide, 8192-deep memory. After this commit, initial assignments where address and/or data are constant (after `generate`) do not incur the cost of intermediate wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant. This results in speedups of orders of magnitude for common memory sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep memory, and only 5.8 s to process a 8-wide, 131072-deep one. As a bonus, this change also results in nontrivial speedups later in the synthesis pipeline, since pass sequencing issues meant that all of these intermediate wires were subject to transformations such as width reduction, even though they existed solely to be constant folded away in `memory_collect`.
2020-01-01 21:18:28 +01:00
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto assign_data = std::make_unique<AstNode>(location, AST_ASSIGN_EQ, std::make_unique<AstNode>(location, AST_IDENTIFIER), mkconst_bits(location, x_bits_data, false));
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT. Before this commit, every initial assignment to a memory generated two wires and four assigns in a process. For unknown reasons (I did not investigate), large amounts of assigns cause quadratic slowdown later in the AST frontend, in processAst/removeSignalFromCaseTree. As a consequence, common and reasonable Verilog code, such as: reg [`WIDTH:0] mem [0:`DEPTH]; integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0; took extremely long time to be processed; around 80 s for a 8-wide, 8192-deep memory. After this commit, initial assignments where address and/or data are constant (after `generate`) do not incur the cost of intermediate wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant. This results in speedups of orders of magnitude for common memory sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep memory, and only 5.8 s to process a 8-wide, 131072-deep one. As a bonus, this change also results in nontrivial speedups later in the synthesis pipeline, since pass sequencing issues meant that all of these intermediate wires were subject to transformations such as width reduction, even though they existed solely to be constant folded away in `memory_collect`.
2020-01-01 21:18:28 +01:00
assign_data->children[0]->str = id_data;
assign_data->children[0]->was_checked = true;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
defNode->children.push_back(std::move(assign_data));
initial import
2013-01-05 11:13:26 +01:00
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
node_data = std::make_unique<AstNode>(location, AST_IDENTIFIER);
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT. Before this commit, every initial assignment to a memory generated two wires and four assigns in a process. For unknown reasons (I did not investigate), large amounts of assigns cause quadratic slowdown later in the AST frontend, in processAst/removeSignalFromCaseTree. As a consequence, common and reasonable Verilog code, such as: reg [`WIDTH:0] mem [0:`DEPTH]; integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0; took extremely long time to be processed; around 80 s for a 8-wide, 8192-deep memory. After this commit, initial assignments where address and/or data are constant (after `generate`) do not incur the cost of intermediate wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant. This results in speedups of orders of magnitude for common memory sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep memory, and only 5.8 s to process a 8-wide, 131072-deep one. As a bonus, this change also results in nontrivial speedups later in the synthesis pipeline, since pass sequencing issues meant that all of these intermediate wires were subject to transformations such as width reduction, even though they existed solely to be constant folded away in `memory_collect`.
2020-01-01 21:18:28 +01:00
node_data->str = id_data;
}
initial import
2013-01-05 11:13:26 +01:00
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto wire_en_owned = std::make_unique<AstNode>(location, AST_WIRE, std::make_unique<AstNode>(location, AST_RANGE, mkconst_int(location, mem_width-1, true), mkconst_int(location, 0, true)));
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto* wire_en = wire_en_owned.get();
verilog: Emit $meminit_v2 cell. Fixes #2447.
2021-05-21 02:27:06 +02:00
wire_en->str = id_en;
wire_en->was_checked = true;
current_scope[wire_en->str] = wire_en;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_ast_mod->children.push_back(std::move(wire_en_owned));
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (wire_en->simplify(true, 1, -1, false)) { }
initial import
2013-01-05 11:13:26 +01:00
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto assign_en_first = std::make_unique<AstNode>(location, AST_ASSIGN_EQ, std::make_unique<AstNode>(location, AST_IDENTIFIER), mkconst_int(location, 0, false, mem_width));
verilog: Emit $meminit_v2 cell. Fixes #2447.
2021-05-21 02:27:06 +02:00
assign_en_first->children[0]->str = id_en;
assign_en_first->children[0]->was_checked = true;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
defNode->children.push_back(std::move(assign_en_first));
verilog: Emit $meminit_v2 cell. Fixes #2447.
2021-05-21 02:27:06 +02:00
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto node_en = std::make_unique<AstNode>(location, AST_IDENTIFIER);
verilog: Emit $meminit_v2 cell. Fixes #2447.
2021-05-21 02:27:06 +02:00
node_en->str = id_en;
initial import
2013-01-05 11:13:26 +01:00
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT. Before this commit, every initial assignment to a memory generated two wires and four assigns in a process. For unknown reasons (I did not investigate), large amounts of assigns cause quadratic slowdown later in the AST frontend, in processAst/removeSignalFromCaseTree. As a consequence, common and reasonable Verilog code, such as: reg [`WIDTH:0] mem [0:`DEPTH]; integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0; took extremely long time to be processed; around 80 s for a 8-wide, 8192-deep memory. After this commit, initial assignments where address and/or data are constant (after `generate`) do not incur the cost of intermediate wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant. This results in speedups of orders of magnitude for common memory sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep memory, and only 5.8 s to process a 8-wide, 131072-deep one. As a bonus, this change also results in nontrivial speedups later in the synthesis pipeline, since pass sequencing issues meant that all of these intermediate wires were subject to transformations such as width reduction, even though they existed solely to be constant folded away in `memory_collect`.
2020-01-01 21:18:28 +01:00
if (!defNode->children.empty())
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_top_block->children.insert(current_top_block->children.begin(), std::move(defNode));
initial import
2013-01-05 11:13:26 +01:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
std::unique_ptr<AstNode> assign_data = nullptr;
std::unique_ptr<AstNode> assign_en = nullptr;
Added support for constant bit- or part-select for memory writes
2014-07-17 13:13:21 +02:00
if (children[0]->children.size() == 2)
{
if (children[0]->children[1]->range_valid)
{
int offset = children[0]->children[1]->range_right;
int width = children[0]->children[1]->range_left - offset + 1;
Fixed bug with memories that do not have a down-to-zero data width
2016-08-22 14:27:46 +02:00
offset -= mem_data_range_offset;
initial import
2013-01-05 11:13:26 +01:00
Added support for constant bit- or part-select for memory writes
2014-07-17 13:13:21 +02:00
std::vector<RTLIL::State> padding_x(offset, RTLIL::State::Sx);
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
assign_data = std::make_unique<AstNode>(location, AST_ASSIGN_EQ, std::make_unique<AstNode>(location, AST_IDENTIFIER),
std::make_unique<AstNode>(location, AST_CONCAT, mkconst_bits(location, padding_x, false), children[1]->clone()));
Added support for constant bit- or part-select for memory writes
2014-07-17 13:13:21 +02:00
assign_data->children[0]->str = id_data;
Modified errors into warnings No longer false warnings for memories and assertions
2018-06-05 16:44:24 +02:00
assign_data->children[0]->was_checked = true;
Added support for constant bit- or part-select for memory writes
2014-07-17 13:13:21 +02:00
verilog: Emit $meminit_v2 cell. Fixes #2447.
2021-05-21 02:27:06 +02:00
for (int i = 0; i < mem_width; i++)
set_bits_en[i] = offset <= i && i < offset+width ? RTLIL::State::S1 : RTLIL::State::S0;
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
assign_en = std::make_unique<AstNode>(location, AST_ASSIGN_EQ, std::make_unique<AstNode>(location, AST_IDENTIFIER), mkconst_bits(location, set_bits_en, false));
verilog: Emit $meminit_v2 cell. Fixes #2447.
2021-05-21 02:27:06 +02:00
assign_en->children[0]->str = id_en;
assign_en->children[0]->was_checked = true;
Added support for constant bit- or part-select for memory writes
2014-07-17 13:13:21 +02:00
}
else
{
frontends/ast: More usage of auto For consistency.
2025-08-08 07:10:16 +02:00
auto& the_range = children[0]->children[1];
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
std::unique_ptr<AstNode> offset_ast;
ast/simplify: Factor out helper to determine range width
2023-04-04 11:34:17 +02:00
int width;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
if (!try_determine_range_width(the_range.get(), width))
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
ast/simplify: Factor out helper to determine range width
2023-04-04 11:34:17 +02:00
if (the_range->children.size() >= 2)
offset_ast = the_range->children[1]->clone();
else
offset_ast = the_range->children[0]->clone();
Implemented dynamic bit-/part-select for memory writes
2014-07-17 16:49:23 +02:00
Fixed bug with memories that do not have a down-to-zero data width
2016-08-22 14:27:46 +02:00
if (mem_data_range_offset)
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
offset_ast = std::make_unique<AstNode>(location, AST_SUB, std::move(offset_ast), mkconst_int(location, mem_data_range_offset, true));
Fixed bug with memories that do not have a down-to-zero data width
2016-08-22 14:27:46 +02:00
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
assign_data = std::make_unique<AstNode>(location, AST_ASSIGN_EQ, std::make_unique<AstNode>(location, AST_IDENTIFIER),
std::make_unique<AstNode>(location, AST_SHIFT_LEFT, children[1]->clone(), offset_ast->clone()));
Implemented dynamic bit-/part-select for memory writes
2014-07-17 16:49:23 +02:00
assign_data->children[0]->str = id_data;
Modified errors into warnings No longer false warnings for memories and assertions
2018-06-05 16:44:24 +02:00
assign_data->children[0]->was_checked = true;
Implemented dynamic bit-/part-select for memory writes
2014-07-17 16:49:23 +02:00
verilog: Emit $meminit_v2 cell. Fixes #2447.
2021-05-21 02:27:06 +02:00
for (int i = 0; i < mem_width; i++)
set_bits_en[i] = i < width ? RTLIL::State::S1 : RTLIL::State::S0;
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
assign_en = std::make_unique<AstNode>(location, AST_ASSIGN_EQ, std::make_unique<AstNode>(location, AST_IDENTIFIER),
std::make_unique<AstNode>(location, AST_SHIFT_LEFT, mkconst_bits(location, set_bits_en, false), offset_ast->clone()));
verilog: Emit $meminit_v2 cell. Fixes #2447.
2021-05-21 02:27:06 +02:00
assign_en->children[0]->str = id_en;
assign_en->children[0]->was_checked = true;
Added support for constant bit- or part-select for memory writes
2014-07-17 13:13:21 +02:00
}
}
else
{
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT. Before this commit, every initial assignment to a memory generated two wires and four assigns in a process. For unknown reasons (I did not investigate), large amounts of assigns cause quadratic slowdown later in the AST frontend, in processAst/removeSignalFromCaseTree. As a consequence, common and reasonable Verilog code, such as: reg [`WIDTH:0] mem [0:`DEPTH]; integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0; took extremely long time to be processed; around 80 s for a 8-wide, 8192-deep memory. After this commit, initial assignments where address and/or data are constant (after `generate`) do not incur the cost of intermediate wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant. This results in speedups of orders of magnitude for common memory sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep memory, and only 5.8 s to process a 8-wide, 131072-deep one. As a bonus, this change also results in nontrivial speedups later in the synthesis pipeline, since pass sequencing issues meant that all of these intermediate wires were subject to transformations such as width reduction, even though they existed solely to be constant folded away in `memory_collect`.
2020-01-01 21:18:28 +01:00
if (!(children[0]->children.size() == 1 && children[1]->isConst())) {
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
assign_data = std::make_unique<AstNode>(location, AST_ASSIGN_EQ, std::make_unique<AstNode>(location, AST_IDENTIFIER), children[1]->clone());
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT. Before this commit, every initial assignment to a memory generated two wires and four assigns in a process. For unknown reasons (I did not investigate), large amounts of assigns cause quadratic slowdown later in the AST frontend, in processAst/removeSignalFromCaseTree. As a consequence, common and reasonable Verilog code, such as: reg [`WIDTH:0] mem [0:`DEPTH]; integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0; took extremely long time to be processed; around 80 s for a 8-wide, 8192-deep memory. After this commit, initial assignments where address and/or data are constant (after `generate`) do not incur the cost of intermediate wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant. This results in speedups of orders of magnitude for common memory sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep memory, and only 5.8 s to process a 8-wide, 131072-deep one. As a bonus, this change also results in nontrivial speedups later in the synthesis pipeline, since pass sequencing issues meant that all of these intermediate wires were subject to transformations such as width reduction, even though they existed solely to be constant folded away in `memory_collect`.
2020-01-01 21:18:28 +01:00
assign_data->children[0]->str = id_data;
assign_data->children[0]->was_checked = true;
}
Added support for constant bit- or part-select for memory writes
2014-07-17 13:13:21 +02:00
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
assign_en = std::make_unique<AstNode>(location, AST_ASSIGN_EQ, std::make_unique<AstNode>(location, AST_IDENTIFIER), mkconst_bits(location, set_bits_en, false));
verilog: Emit $meminit_v2 cell. Fixes #2447.
2021-05-21 02:27:06 +02:00
assign_en->children[0]->str = id_en;
assign_en->children[0]->was_checked = true;
Added support for constant bit- or part-select for memory writes
2014-07-17 13:13:21 +02:00
}
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT. Before this commit, every initial assignment to a memory generated two wires and four assigns in a process. For unknown reasons (I did not investigate), large amounts of assigns cause quadratic slowdown later in the AST frontend, in processAst/removeSignalFromCaseTree. As a consequence, common and reasonable Verilog code, such as: reg [`WIDTH:0] mem [0:`DEPTH]; integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0; took extremely long time to be processed; around 80 s for a 8-wide, 8192-deep memory. After this commit, initial assignments where address and/or data are constant (after `generate`) do not incur the cost of intermediate wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant. This results in speedups of orders of magnitude for common memory sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep memory, and only 5.8 s to process a 8-wide, 131072-deep one. As a bonus, this change also results in nontrivial speedups later in the synthesis pipeline, since pass sequencing issues meant that all of these intermediate wires were subject to transformations such as width reduction, even though they existed solely to be constant folded away in `memory_collect`.
2020-01-01 21:18:28 +01:00
if (assign_data)
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
newNode->children.push_back(std::move(assign_data));
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT. Before this commit, every initial assignment to a memory generated two wires and four assigns in a process. For unknown reasons (I did not investigate), large amounts of assigns cause quadratic slowdown later in the AST frontend, in processAst/removeSignalFromCaseTree. As a consequence, common and reasonable Verilog code, such as: reg [`WIDTH:0] mem [0:`DEPTH]; integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0; took extremely long time to be processed; around 80 s for a 8-wide, 8192-deep memory. After this commit, initial assignments where address and/or data are constant (after `generate`) do not incur the cost of intermediate wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant. This results in speedups of orders of magnitude for common memory sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep memory, and only 5.8 s to process a 8-wide, 131072-deep one. As a bonus, this change also results in nontrivial speedups later in the synthesis pipeline, since pass sequencing issues meant that all of these intermediate wires were subject to transformations such as width reduction, even though they existed solely to be constant folded away in `memory_collect`.
2020-01-01 21:18:28 +01:00
if (assign_en)
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
newNode->children.push_back(std::move(assign_en));
initial import
2013-01-05 11:13:26 +01:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
std::unique_ptr<AstNode> wrnode;
verilog: Emit $meminit_v2 cell. Fixes #2447.
2021-05-21 02:27:06 +02:00
if (current_always->type == AST_INITIAL)
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
wrnode = std::make_unique<AstNode>(location, AST_MEMINIT, std::move(node_addr), std::move(node_data), std::move(node_en), mkconst_int(location, 1, false));
verilog: Emit $meminit_v2 cell. Fixes #2447.
2021-05-21 02:27:06 +02:00
else
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
wrnode = std::make_unique<AstNode>(location, AST_MEMWR, std::move(node_addr), std::move(node_data), std::move(node_en));
initial import
2013-01-05 11:13:26 +01:00
wrnode->str = children[0]->str;
Various fixes for memories with offsets
2015-02-14 14:21:15 +01:00
wrnode->id2ast = children[0]->id2ast;
verilog: Use proc memory writes in the frontend.
2021-02-23 16:48:29 +01:00
wrnode->location = location;
if (wrnode->type == AST_MEMWR) {
int portid = current_memwr_count[wrnode->str]++;
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
wrnode->children.push_back(mkconst_int(location, portid, false));
verilog: Use proc memory writes in the frontend.
2021-02-23 16:48:29 +01:00
std::vector<RTLIL::State> priority_mask;
for (int i = 0; i < portid; i++) {
bool has_prio = current_memwr_visible[wrnode->str].count(i);
priority_mask.push_back(State(has_prio));
}
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
wrnode->children.push_back(mkconst_bits(location, priority_mask, false));
verilog: Use proc memory writes in the frontend.
2021-02-23 16:48:29 +01:00
current_memwr_visible[wrnode->str].insert(portid);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_always->children.push_back(std::move(wrnode));
verilog: Use proc memory writes in the frontend.
2021-02-23 16:48:29 +01:00
} else {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_ast_mod->children.push_back(std::move(wrnode));
verilog: Use proc memory writes in the frontend.
2021-02-23 16:48:29 +01:00
}
initial import
2013-01-05 11:13:26 +01:00
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT. Before this commit, every initial assignment to a memory generated two wires and four assigns in a process. For unknown reasons (I did not investigate), large amounts of assigns cause quadratic slowdown later in the AST frontend, in processAst/removeSignalFromCaseTree. As a consequence, common and reasonable Verilog code, such as: reg [`WIDTH:0] mem [0:`DEPTH]; integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0; took extremely long time to be processed; around 80 s for a 8-wide, 8192-deep memory. After this commit, initial assignments where address and/or data are constant (after `generate`) do not incur the cost of intermediate wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant. This results in speedups of orders of magnitude for common memory sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep memory, and only 5.8 s to process a 8-wide, 131072-deep one. As a bonus, this change also results in nontrivial speedups later in the synthesis pipeline, since pass sequencing issues meant that all of these intermediate wires were subject to transformations such as width reduction, even though they existed solely to be constant folded away in `memory_collect`.
2020-01-01 21:18:28 +01:00
if (newNode->children.empty()) {
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = std::make_unique<AstNode>(location);
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT. Before this commit, every initial assignment to a memory generated two wires and four assigns in a process. For unknown reasons (I did not investigate), large amounts of assigns cause quadratic slowdown later in the AST frontend, in processAst/removeSignalFromCaseTree. As a consequence, common and reasonable Verilog code, such as: reg [`WIDTH:0] mem [0:`DEPTH]; integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0; took extremely long time to be processed; around 80 s for a 8-wide, 8192-deep memory. After this commit, initial assignments where address and/or data are constant (after `generate`) do not incur the cost of intermediate wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant. This results in speedups of orders of magnitude for common memory sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep memory, and only 5.8 s to process a 8-wide, 131072-deep one. As a bonus, this change also results in nontrivial speedups later in the synthesis pipeline, since pass sequencing issues meant that all of these intermediate wires were subject to transformations such as width reduction, even though they existed solely to be constant folded away in `memory_collect`.
2020-01-01 21:18:28 +01:00
}
initial import
2013-01-05 11:13:26 +01:00
goto apply_newNode;
}
// replace function and task calls with the code from the function or task
if ((type == AST_FCALL || type == AST_TCALL) && !str.empty())
{
Added support for $clog2 system function
2013-12-04 21:19:54 +01:00
if (type == AST_FCALL)
{
Added $initstate cell type and vlog function
2016-07-21 14:23:22 +02:00
if (str == "\\$initstate")
{
int myidx = autoidx++;
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto wire_owned = std::make_unique<AstNode>(location, AST_WIRE);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto* wire = wire_owned.get();
current_ast_mod->children.push_back(std::move(wire_owned));
Added $initstate cell type and vlog function
2016-07-21 14:23:22 +02:00
wire->str = stringf("$initstate$%d_wire", myidx);
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (wire->simplify(true, 1, -1, false)) { }
Added $initstate cell type and vlog function
2016-07-21 14:23:22 +02:00
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto cell = std::make_unique<AstNode>(location, AST_CELL, std::make_unique<AstNode>(location, AST_CELLTYPE), std::make_unique<AstNode>(location, AST_ARGUMENT, std::make_unique<AstNode>(location, AST_IDENTIFIER)));
Added $initstate cell type and vlog function
2016-07-21 14:23:22 +02:00
cell->str = stringf("$initstate$%d", myidx);
cell->children[0]->str = "$initstate";
cell->children[1]->str = "\\Y";
cell->children[1]->children[0]->str = wire->str;
cell->children[1]->children[0]->id2ast = wire;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_ast_mod->children.push_back(std::move(cell));
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (cell->simplify(true, 1, -1, false)) { }
Added $initstate cell type and vlog function
2016-07-21 14:23:22 +02:00
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = std::make_unique<AstNode>(location, AST_IDENTIFIER);
Added $initstate cell type and vlog function
2016-07-21 14:23:22 +02:00
newNode->str = wire->str;
newNode->id2ast = wire;
goto apply_newNode;
}
Added $past, $stable, $rose, $fell SVA functions
2016-09-19 01:30:07 +02:00
if (str == "\\$past")
{
Fix handling of expression width in $past, fixes #810 Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 17:55:33 +01:00
if (width_hint < 0)
Added $past, $stable, $rose, $fell SVA functions
2016-09-19 01:30:07 +02:00
goto replace_fcall_later;
int num_steps = 1;
if (GetSize(children) != 1 && GetSize(children) != 2)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("System function %s got %d arguments, expected 1 or 2.\n",
Various indenting fixes in AST front-end (mostly space vs tab issues) Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-04 10:19:32 +01:00
RTLIL::unescape_id(str).c_str(), int(children.size()));
Added $past, $stable, $rose, $fell SVA functions
2016-09-19 01:30:07 +02:00
if (!current_always_clocked)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("System function %s is only allowed in clocked blocks.\n",
Various indenting fixes in AST front-end (mostly space vs tab issues) Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-04 10:19:32 +01:00
RTLIL::unescape_id(str).c_str());
Added $past, $stable, $rose, $fell SVA functions
2016-09-19 01:30:07 +02:00
if (GetSize(children) == 2)
{
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto buf = children[1]->clone();
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (buf->simplify(true, stage, -1, false)) { }
Added $past, $stable, $rose, $fell SVA functions
2016-09-19 01:30:07 +02:00
if (buf->type != AST_CONSTANT)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Failed to evaluate system function `%s' with non-constant value.\n", str.c_str());
Added $past, $stable, $rose, $fell SVA functions
2016-09-19 01:30:07 +02:00
num_steps = buf->asInt(true);
}
AstNode *block = nullptr;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : current_always->children)
Added $past, $stable, $rose, $fell SVA functions
2016-09-19 01:30:07 +02:00
if (child->type == AST_BLOCK)
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
block = child.get();
Added $past, $stable, $rose, $fell SVA functions
2016-09-19 01:30:07 +02:00
log_assert(block != nullptr);
Fix segfault in AST simplify (as proposed by Dan Gisselquist) Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-18 17:49:38 +01:00
if (num_steps == 0) {
newNode = children[0]->clone();
goto apply_newNode;
}
Added $past, $stable, $rose, $fell SVA functions
2016-09-19 01:30:07 +02:00
int myidx = autoidx++;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
AstNode* outreg = nullptr;
Added $past, $stable, $rose, $fell SVA functions
2016-09-19 01:30:07 +02:00
for (int i = 0; i < num_steps; i++)
{
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto reg_owned = std::make_unique<AstNode>(location, AST_WIRE, std::make_unique<AstNode>(location, AST_RANGE,
mkconst_int(location, width_hint-1, true), mkconst_int(location, 0, true)));
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto* reg = reg_owned.get();
current_ast_mod->children.push_back(std::move(reg_owned));
Added $past, $stable, $rose, $fell SVA functions
2016-09-19 01:30:07 +02:00
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
reg->str = stringf("$past$%s:%d$%d$%d", RTLIL::encode_filename(*location.begin.filename).c_str(), location.begin.line, myidx, i);
Added $past, $stable, $rose, $fell SVA functions
2016-09-19 01:30:07 +02:00
reg->is_reg = true;
verilog: fix $past's signedness
2022-05-24 17:18:53 +02:00
reg->is_signed = sign_hint;
Added $past, $stable, $rose, $fell SVA functions
2016-09-19 01:30:07 +02:00
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (reg->simplify(true, 1, -1, false)) { }
Added $past, $stable, $rose, $fell SVA functions
2016-09-19 01:30:07 +02:00
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto regid = std::make_unique<AstNode>(location, AST_IDENTIFIER);
Added $past, $stable, $rose, $fell SVA functions
2016-09-19 01:30:07 +02:00
regid->str = reg->str;
regid->id2ast = reg;
Fixed remaining cases where we check fo wire reg/wire incorrect assignments on Yosys-generated assignments. In this case, offending code was: module top(input in, output out); function func; input arg; func = arg; endfunction assign out = func(in); endmodule
2018-09-18 00:23:40 +02:00
regid->was_checked = true;
Added $past, $stable, $rose, $fell SVA functions
2016-09-19 01:30:07 +02:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
std::unique_ptr<AstNode> rhs = nullptr;
Added $past, $stable, $rose, $fell SVA functions
2016-09-19 01:30:07 +02:00
if (outreg == nullptr) {
rhs = children.at(0)->clone();
} else {
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
rhs = std::make_unique<AstNode>(location, AST_IDENTIFIER);
Added $past, $stable, $rose, $fell SVA functions
2016-09-19 01:30:07 +02:00
rhs->str = outreg->str;
rhs->id2ast = outreg;
}
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
block->children.push_back(std::make_unique<AstNode>(location, AST_ASSIGN_LE, std::move(regid), std::move(rhs)));
Added $past, $stable, $rose, $fell SVA functions
2016-09-19 01:30:07 +02:00
outreg = reg;
}
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = std::make_unique<AstNode>(location, AST_IDENTIFIER);
Added $past, $stable, $rose, $fell SVA functions
2016-09-19 01:30:07 +02:00
newNode->str = outreg->str;
newNode->id2ast = outreg;
goto apply_newNode;
}
Add read_verilog $changed support Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-01 19:41:35 +02:00
if (str == "\\$stable" || str == "\\$rose" || str == "\\$fell" || str == "\\$changed")
Added $past, $stable, $rose, $fell SVA functions
2016-09-19 01:30:07 +02:00
{
if (GetSize(children) != 1)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("System function %s got %d arguments, expected 1.\n",
Various indenting fixes in AST front-end (mostly space vs tab issues) Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-04 10:19:32 +01:00
RTLIL::unescape_id(str).c_str(), int(children.size()));
Added $past, $stable, $rose, $fell SVA functions
2016-09-19 01:30:07 +02:00
if (!current_always_clocked)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("System function %s is only allowed in clocked blocks.\n",
Various indenting fixes in AST front-end (mostly space vs tab issues) Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-04 10:19:32 +01:00
RTLIL::unescape_id(str).c_str());
Added $past, $stable, $rose, $fell SVA functions
2016-09-19 01:30:07 +02:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto present = children.at(0)->clone();
auto past = clone();
Added $past, $stable, $rose, $fell SVA functions
2016-09-19 01:30:07 +02:00
past->str = "\\$past";
if (str == "\\$stable")
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = std::make_unique<AstNode>(location, AST_EQ, std::move(past), std::move(present));
Added $past, $stable, $rose, $fell SVA functions
2016-09-19 01:30:07 +02:00
Add read_verilog $changed support Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-01 19:41:35 +02:00
else if (str == "\\$changed")
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = std::make_unique<AstNode>(location, AST_NE, std::move(past), std::move(present));
Add read_verilog $changed support Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-01 19:41:35 +02:00
Added $past, $stable, $rose, $fell SVA functions
2016-09-19 01:30:07 +02:00
else if (str == "\\$rose")
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = std::make_unique<AstNode>(location, AST_LOGIC_AND,
std::make_unique<AstNode>(location, AST_LOGIC_NOT, std::make_unique<AstNode>(location, AST_BIT_AND, std::move(past), mkconst_int(location, 1, false))),
std::make_unique<AstNode>(location, AST_BIT_AND, std::move(present), mkconst_int(location, 1, false)));
Added $past, $stable, $rose, $fell SVA functions
2016-09-19 01:30:07 +02:00
else if (str == "\\$fell")
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = std::make_unique<AstNode>(location, AST_LOGIC_AND,
std::make_unique<AstNode>(location, AST_BIT_AND, std::move(past), mkconst_int(location, 1, false)),
std::make_unique<AstNode>(location, AST_LOGIC_NOT, std::make_unique<AstNode>(location, AST_BIT_AND, std::move(present), mkconst_int(location, 1, false))));
Added $past, $stable, $rose, $fell SVA functions
2016-09-19 01:30:07 +02:00
else
log_abort();
goto apply_newNode;
}
Added $anyseq cell type
2016-10-14 15:24:03 +02:00
// $anyconst and $anyseq are mapped in AstNode::genRTLIL()
Add $allconst and $allseq cell types Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-23 13:14:47 +01:00
if (str == "\\$anyconst" || str == "\\$anyseq" || str == "\\$allconst" || str == "\\$allseq") {
Added $past, $stable, $rose, $fell SVA functions
2016-09-19 01:30:07 +02:00
recursion_counter--;
Added $anyconst and $aconst
2016-07-27 15:41:22 +02:00
return false;
Added $past, $stable, $rose, $fell SVA functions
2016-09-19 01:30:07 +02:00
}
Added $anyconst and $aconst
2016-07-27 15:41:22 +02:00
Added support for $clog2 system function
2013-12-04 21:19:54 +01:00
if (str == "\\$clog2")
{
Added support for math functions
2014-06-14 13:36:23 +02:00
if (children.size() != 1)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("System function %s got %d arguments, expected 1.\n",
Various indenting fixes in AST front-end (mostly space vs tab issues) Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-04 10:19:32 +01:00
RTLIL::unescape_id(str).c_str(), int(children.size()));
Added support for math functions
2014-06-14 13:36:23 +02:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto buf = children[0]->clone();
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (buf->simplify(true, stage, width_hint, sign_hint)) { }
Fixed typo in frontends/ast/simplify.cc
2014-01-12 21:04:42 +01:00
if (buf->type != AST_CONSTANT)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Failed to evaluate system function `%s' with non-constant value.\n", str.c_str());
Added support for $clog2 system function
2013-12-04 21:19:54 +01:00
RTLIL::Const arg_value = buf->bitsAsConst();
Another $clog2 bugfix
2014-09-08 12:25:23 +02:00
if (arg_value.as_bool())
Renamed SIZE() to GetSize() because of name collision on Win32
2014-10-10 16:59:44 +02:00
arg_value = const_sub(arg_value, 1, false, false, GetSize(arg_value));
Fixed two memory leaks in ast simplify
2014-07-25 13:07:31 +02:00
Added support for $clog2 system function
2013-12-04 21:19:54 +01:00
uint32_t result = 0;
Reduce comparisons of size_t and int `Const::size()` returns int, so change iterators that use it to `auto` instead of `size_t`. For cases where size is being explicitly cast to `int`, use the wrapper that we already have instead: `Yosys::GetSize()`.
2024-11-29 00:31:34 +01:00
for (auto i = 0; i < arg_value.size(); i++)
rtlil: represent Const strings as std::string
2024-10-09 19:39:45 +02:00
if (arg_value.at(i) == RTLIL::State::S1)
Fixed $clog2 (off by one error)
2014-09-06 19:31:04 +02:00
result = i + 1;
Added support for $clog2 system function
2013-12-04 21:19:54 +01:00
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = mkconst_int(location, result, true);
Added support for $clog2 system function
2013-12-04 21:19:54 +01:00
goto apply_newNode;
Fixed name resolution of local tasks and functions in generate block
2013-11-20 11:05:58 +01:00
}
Add $size() function. At the moment it works only on expressions, not on memories.
2017-09-26 05:25:42 +02:00
Add support for $dimensions and $unpacked_dimensions
2023-12-28 00:23:59 +01:00
if (str == "\\$dimensions" || str == "\\$unpacked_dimensions" ||
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
str == "\\$increment" || str == "\\$size" || str == "\\$bits" || str == "\\$high" || str == "\\$low" || str == "\\$left" || str == "\\$right")
Add $size() function. At the moment it works only on expressions, not on memories.
2017-09-26 05:25:42 +02:00
{
$size() seems to work now with or without the optional parameter. Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated.
2017-09-26 18:18:25 +02:00
int dim = 1;
Add support for $dimensions and $unpacked_dimensions
2023-12-28 00:23:59 +01:00
if (str == "\\$dimensions" || str == "\\$unpacked_dimensions" || str == "\\$bits") {
Added $high(), $low(), $left(), $right()
2020-09-15 19:49:52 +02:00
if (children.size() != 1)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("System function %s got %d arguments, expected 1.\n",
Added $high(), $low(), $left(), $right()
2020-09-15 19:49:52 +02:00
RTLIL::unescape_id(str).c_str(), int(children.size()));
} else {
if (children.size() != 1 && children.size() != 2)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("System function %s got %d arguments, expected 1 or 2.\n",
Added $high(), $low(), $left(), $right()
2020-09-15 19:49:52 +02:00
RTLIL::unescape_id(str).c_str(), int(children.size()));
if (children.size() == 2) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto buf = children[1]->clone();
Added $high(), $low(), $left(), $right()
2020-09-15 19:49:52 +02:00
// Evaluate constant expression
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (buf->simplify(true, stage, width_hint, sign_hint)) { }
Added $high(), $low(), $left(), $right()
2020-09-15 19:49:52 +02:00
dim = buf->asInt(false);
}
$size() seems to work now with or without the optional parameter. Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated.
2017-09-26 18:18:25 +02:00
}
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto buf = children[0]->clone();
Added $bits() for memories as well.
2017-09-26 08:11:25 +02:00
int mem_depth = 1;
Added $high(), $low(), $left(), $right()
2020-09-15 19:49:52 +02:00
int result, high = 0, low = 0, left = 0, right = 0, width = 1; // defaults for a simple wire
Add support for $dimensions and $unpacked_dimensions
2023-12-28 00:23:59 +01:00
int expr_dimensions = 0, expr_unpacked_dimensions = 0;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
AstNode *id_ast = nullptr;
$size() seems to work now with or without the optional parameter. Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated.
2017-09-26 18:18:25 +02:00
Add $size() function. At the moment it works only on expressions, not on memories.
2017-09-26 05:25:42 +02:00
buf->detectSignWidth(width_hint, sign_hint);
$size() now works correctly for all cases! It seems the issues was that AST_MULTIRANGE is converted into a multirange_dimensions[] array on the AST_MEMORY node directly.
2017-09-26 19:34:24 +02:00
$size() seems to work now with or without the optional parameter. Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated.
2017-09-26 18:18:25 +02:00
if (buf->type == AST_IDENTIFIER) {
id_ast = buf->id2ast;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
if (id_ast == nullptr && current_scope.count(buf->str))
$size() seems to work now with or without the optional parameter. Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated.
2017-09-26 18:18:25 +02:00
id_ast = current_scope.at(buf->str);
if (!id_ast)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Failed to resolve identifier %s for width detection!\n", buf->str.c_str());
Support for data and array queries on struct/union item expressions For now, $bits, $left, $right, $low, $high, and $size are supported.
2023-02-09 19:27:51 +01:00
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
if (id_ast->type == AST_WIRE || id_ast->type == AST_MEMORY) {
// Check for item in packed struct / union
AstNode *item_node = buf->get_struct_member();
if (item_node)
id_ast = item_node;
Support for data and array queries on struct/union item expressions For now, $bits, $left, $right, $low, $high, and $size are supported.
2023-02-09 19:27:51 +01:00
// The dimension of the original array expression is saved in the 'integer' field
dim += buf->integer;
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
int dims = GetSize(id_ast->dimensions);
// TODO: IEEE Std 1800-2017 20.7: "If the first argument to an array query function would cause $dimensions to return 0
// or if the second argument is out of range, then 'x shall be returned."
if (dim < 1 || dim > dims)
input_error("Dimension %d out of range in `%s', as it only has %d dimensions!\n", dim, id_ast->str.c_str(), dims);
Add support for $dimensions and $unpacked_dimensions
2023-12-28 00:23:59 +01:00
expr_dimensions = dims - dim + 1;
expr_unpacked_dimensions = std::max(id_ast->unpacked_dimensions - dim + 1, 0);
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
right = low = id_ast->dimensions[dim - 1].range_right;
left = high = low + id_ast->dimensions[dim - 1].range_width - 1;
if (id_ast->dimensions[dim - 1].range_swapped) {
std::swap(left, right);
}
for (int i = dim; i < dims; i++) {
mem_depth *= id_ast->dimensions[i].range_width;
Added $bits() for memories as well.
2017-09-26 08:11:25 +02:00
}
}
Added $high(), $low(), $left(), $right()
2020-09-15 19:49:52 +02:00
width = high - low + 1;
} else {
width = width_hint;
Add support for $dimensions and $unpacked_dimensions
2023-12-28 00:23:59 +01:00
right = low = 0;
left = high = width - 1;
expr_dimensions = 1;
Added $bits() for memories as well.
2017-09-26 08:11:25 +02:00
}
Add support for $dimensions and $unpacked_dimensions
2023-12-28 00:23:59 +01:00
if (str == "\\$dimensions")
result = expr_dimensions;
else if (str == "\\$unpacked_dimensions")
result = expr_unpacked_dimensions;
else if (str == "\\$high")
Added $high(), $low(), $left(), $right()
2020-09-15 19:49:52 +02:00
result = high;
else if (str == "\\$low")
result = low;
else if (str == "\\$left")
result = left;
else if (str == "\\$right")
result = right;
Add support for $increment
2023-12-27 22:00:13 +01:00
else if (str == "\\$increment")
result = left >= right ? 1 : -1;
Added $high(), $low(), $left(), $right()
2020-09-15 19:49:52 +02:00
else if (str == "\\$size")
result = width;
Support for data and array queries on struct/union item expressions For now, $bits, $left, $right, $low, $high, and $size are supported.
2023-02-09 19:27:51 +01:00
else { // str == "\\$bits"
Added $high(), $low(), $left(), $right()
2020-09-15 19:49:52 +02:00
result = width * mem_depth;
}
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = mkconst_int(location, result, true);
Add $size() function. At the moment it works only on expressions, not on memories.
2017-09-26 05:25:42 +02:00
goto apply_newNode;
}
Added support for $clog2 system function
2013-12-04 21:19:54 +01:00
Added support for math functions
2014-06-14 13:36:23 +02:00
if (str == "\\$ln" || str == "\\$log10" || str == "\\$exp" || str == "\\$sqrt" || str == "\\$pow" ||
str == "\\$floor" || str == "\\$ceil" || str == "\\$sin" || str == "\\$cos" || str == "\\$tan" ||
str == "\\$asin" || str == "\\$acos" || str == "\\$atan" || str == "\\$atan2" || str == "\\$hypot" ||
Added Verilog $rtoi and $itor support
2017-01-03 17:40:58 +01:00
str == "\\$sinh" || str == "\\$cosh" || str == "\\$tanh" || str == "\\$asinh" || str == "\\$acosh" || str == "\\$atanh" ||
str == "\\$rtoi" || str == "\\$itor")
Added support for math functions
2014-06-14 13:36:23 +02:00
{
bool func_with_two_arguments = str == "\\$pow" || str == "\\$atan2" || str == "\\$hypot";
double x = 0, y = 0;
if (func_with_two_arguments) {
if (children.size() != 2)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("System function %s got %d arguments, expected 2.\n",
Various indenting fixes in AST front-end (mostly space vs tab issues) Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-04 10:19:32 +01:00
RTLIL::unescape_id(str).c_str(), int(children.size()));
Added support for math functions
2014-06-14 13:36:23 +02:00
} else {
if (children.size() != 1)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("System function %s got %d arguments, expected 1.\n",
Various indenting fixes in AST front-end (mostly space vs tab issues) Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-04 10:19:32 +01:00
RTLIL::unescape_id(str).c_str(), int(children.size()));
Added support for math functions
2014-06-14 13:36:23 +02:00
}
if (children.size() >= 1) {
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (children[0]->simplify(true, stage, width_hint, sign_hint)) { }
Added support for math functions
2014-06-14 13:36:23 +02:00
if (!children[0]->isConst())
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Failed to evaluate system function `%s' with non-constant argument.\n",
Various indenting fixes in AST front-end (mostly space vs tab issues) Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-04 10:19:32 +01:00
RTLIL::unescape_id(str).c_str());
Added support for math functions
2014-06-14 13:36:23 +02:00
int child_width_hint = width_hint;
bool child_sign_hint = sign_hint;
children[0]->detectSignWidth(child_width_hint, child_sign_hint);
x = children[0]->asReal(child_sign_hint);
}
if (children.size() >= 2) {
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (children[1]->simplify(true, stage, width_hint, sign_hint)) { }
Added support for math functions
2014-06-14 13:36:23 +02:00
if (!children[1]->isConst())
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Failed to evaluate system function `%s' with non-constant argument.\n",
Various indenting fixes in AST front-end (mostly space vs tab issues) Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-04 10:19:32 +01:00
RTLIL::unescape_id(str).c_str());
Added support for math functions
2014-06-14 13:36:23 +02:00
int child_width_hint = width_hint;
bool child_sign_hint = sign_hint;
children[1]->detectSignWidth(child_width_hint, child_sign_hint);
y = children[1]->asReal(child_sign_hint);
}
Added Verilog $rtoi and $itor support
2017-01-03 17:40:58 +01:00
if (str == "\\$rtoi") {
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = AstNode::mkconst_int(location, x, true);
Added Verilog $rtoi and $itor support
2017-01-03 17:40:58 +01:00
} else {
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = std::make_unique<AstNode>(location, AST_REALVALUE);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
if (str == "\\$ln") newNode->realvalue = ::log(x);
Added Verilog $rtoi and $itor support
2017-01-03 17:40:58 +01:00
else if (str == "\\$log10") newNode->realvalue = ::log10(x);
else if (str == "\\$exp") newNode->realvalue = ::exp(x);
else if (str == "\\$sqrt") newNode->realvalue = ::sqrt(x);
else if (str == "\\$pow") newNode->realvalue = ::pow(x, y);
else if (str == "\\$floor") newNode->realvalue = ::floor(x);
else if (str == "\\$ceil") newNode->realvalue = ::ceil(x);
else if (str == "\\$sin") newNode->realvalue = ::sin(x);
else if (str == "\\$cos") newNode->realvalue = ::cos(x);
else if (str == "\\$tan") newNode->realvalue = ::tan(x);
else if (str == "\\$asin") newNode->realvalue = ::asin(x);
else if (str == "\\$acos") newNode->realvalue = ::acos(x);
else if (str == "\\$atan") newNode->realvalue = ::atan(x);
else if (str == "\\$atan2") newNode->realvalue = ::atan2(x, y);
else if (str == "\\$hypot") newNode->realvalue = ::hypot(x, y);
else if (str == "\\$sinh") newNode->realvalue = ::sinh(x);
else if (str == "\\$cosh") newNode->realvalue = ::cosh(x);
else if (str == "\\$tanh") newNode->realvalue = ::tanh(x);
else if (str == "\\$asinh") newNode->realvalue = ::asinh(x);
else if (str == "\\$acosh") newNode->realvalue = ::acosh(x);
else if (str == "\\$atanh") newNode->realvalue = ::atanh(x);
else if (str == "\\$itor") newNode->realvalue = x;
else log_abort();
}
Added support for math functions
2014-06-14 13:36:23 +02:00
goto apply_newNode;
}
ast: Add support for $sformatf system function Signed-off-by: David Shah <dave@ds0.me>
2020-01-19 22:15:51 +01:00
if (str == "\\$sformatf") {
ast: use new format string helpers.
2020-11-29 09:57:07 +01:00
Fmt fmt = processFormat(stage, /*sformat_like=*/true);
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = AstNode::mkconst_str(location, fmt.render());
ast: Add support for $sformatf system function Signed-off-by: David Shah <dave@ds0.me>
2020-01-19 22:15:51 +01:00
goto apply_newNode;
}
Implement $countbits function
2021-02-23 00:55:55 +01:00
if (str == "\\$countbits") {
if (children.size() < 2)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("System function %s got %d arguments, expected at least 2.\n",
Implement $countbits function
2021-02-23 00:55:55 +01:00
RTLIL::unescape_id(str).c_str(), int(children.size()));
std::vector<RTLIL::State> control_bits;
// Determine which bits to count
for (size_t i = 1; i < children.size(); i++) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto& node = children[i];
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (node->simplify(true, stage, -1, false)) { }
Implement $countbits function
2021-02-23 00:55:55 +01:00
if (node->type != AST_CONSTANT)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Failed to evaluate system function `%s' with non-constant control bit argument.\n", str.c_str());
Implement $countbits function
2021-02-23 00:55:55 +01:00
if (node->bits.size() != 1)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Failed to evaluate system function `%s' with control bit width != 1.\n", str.c_str());
Implement $countbits function
2021-02-23 00:55:55 +01:00
control_bits.push_back(node->bits[0]);
}
// Detect width of exp (first argument of $countbits)
int exp_width = -1;
bool exp_sign = false;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto& exp = children[0];
exp->detectSignWidth(exp_width, exp_sign, nullptr);
Implement $countbits function
2021-02-23 00:55:55 +01:00
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = mkconst_int(location, 0, false);
Implement $countbits function
2021-02-23 00:55:55 +01:00
for (int i = 0; i < exp_width; i++) {
// Generate nodes for: exp << i >> ($size(exp) - 1)
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
// ^^ ^^
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto lsh_node = std::make_unique<AstNode>(location, AST_SHIFT_LEFT, exp->clone(), mkconst_int(location, i, false));
auto rsh_node = std::make_unique<AstNode>(location, AST_SHIFT_RIGHT, std::move(lsh_node), mkconst_int(location, exp_width - 1, false));
Implement $countbits function
2021-02-23 00:55:55 +01:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
std::unique_ptr<AstNode> or_node = nullptr;
Implement $countbits function
2021-02-23 00:55:55 +01:00
for (RTLIL::State control_bit : control_bits) {
// Generate node for: (exp << i >> ($size(exp) - 1)) === control_bit
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
// ^^^
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto eq_node = std::make_unique<AstNode>(location, AST_EQX, rsh_node->clone(), mkconst_bits(location, {control_bit}, false));
Implement $countbits function
2021-02-23 00:55:55 +01:00
// Or the result for each checked bit value
if (or_node)
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
or_node = std::make_unique<AstNode>(location, AST_LOGIC_OR, std::move(or_node), std::move(eq_node));
Implement $countbits function
2021-02-23 00:55:55 +01:00
else
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
or_node = std::move(eq_node);
Implement $countbits function
2021-02-23 00:55:55 +01:00
}
// We should have at least one element in control_bits,
// because we checked for the number of arguments above
log_assert(or_node != nullptr);
// Generate node for adding with result of previous bit
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = std::make_unique<AstNode>(location, AST_ADD, std::move(newNode), std::move(or_node));
Implement $countbits function
2021-02-23 00:55:55 +01:00
}
goto apply_newNode;
}
Implement $countones, $isunknown and $onehot{,0}
2021-02-23 01:19:06 +01:00
if (str == "\\$countones" || str == "\\$isunknown" || str == "\\$onehot" || str == "\\$onehot0") {
if (children.size() != 1)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("System function %s got %d arguments, expected 1.\n",
Implement $countones, $isunknown and $onehot{,0}
2021-02-23 01:19:06 +01:00
RTLIL::unescape_id(str).c_str(), int(children.size()));
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto countbits = clone();
Implement $countones, $isunknown and $onehot{,0}
2021-02-23 01:19:06 +01:00
countbits->str = "\\$countbits";
if (str == "\\$countones") {
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
countbits->children.push_back(mkconst_bits(location, {RTLIL::State::S1}, false));
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
newNode = std::move(countbits);
Implement $countones, $isunknown and $onehot{,0}
2021-02-23 01:19:06 +01:00
} else if (str == "\\$isunknown") {
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
countbits->children.push_back(mkconst_bits(location, {RTLIL::Sx}, false));
countbits->children.push_back(mkconst_bits(location, {RTLIL::Sz}, false));
newNode = std::make_unique<AstNode>(location, AST_GT, std::move(countbits), mkconst_int(location, 0, false));
Implement $countones, $isunknown and $onehot{,0}
2021-02-23 01:19:06 +01:00
} else if (str == "\\$onehot") {
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
countbits->children.push_back(mkconst_bits(location, {RTLIL::State::S1}, false));
newNode = std::make_unique<AstNode>(location, AST_EQ, std::move(countbits), mkconst_int(location, 1, false));
Implement $countones, $isunknown and $onehot{,0}
2021-02-23 01:19:06 +01:00
} else if (str == "\\$onehot0") {
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
countbits->children.push_back(mkconst_bits(location, {RTLIL::State::S1}, false));
newNode = std::make_unique<AstNode>(location, AST_LE, std::move(countbits), mkconst_int(location, 1, false));
Implement $countones, $isunknown and $onehot{,0}
2021-02-23 01:19:06 +01:00
} else {
log_abort();
}
goto apply_newNode;
}
Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
2014-08-21 12:43:51 +02:00
if (current_scope.count(str) != 0 && current_scope[str]->type == AST_DPI_FUNCTION)
{
AstNode *dpi_decl = current_scope[str];
std::string rtype, fname;
std::vector<std::string> argtypes;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
std::vector<std::unique_ptr<AstNode>> args;
Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
2014-08-21 12:43:51 +02:00
rtype = RTLIL::unescape_id(dpi_decl->children.at(0)->str);
Added support for DPI function with different names in C and Verilog
2014-08-21 17:22:04 +02:00
fname = RTLIL::unescape_id(dpi_decl->children.at(1)->str);
Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
2014-08-21 12:43:51 +02:00
Renamed SIZE() to GetSize() because of name collision on Win32
2014-10-10 16:59:44 +02:00
for (int i = 2; i < GetSize(dpi_decl->children); i++)
Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
2014-08-21 12:43:51 +02:00
{
Renamed SIZE() to GetSize() because of name collision on Win32
2014-10-10 16:59:44 +02:00
if (i-2 >= GetSize(children))
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Insufficient number of arguments in DPI function call.\n");
Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
2014-08-21 12:43:51 +02:00
argtypes.push_back(RTLIL::unescape_id(dpi_decl->children.at(i)->str));
Added support for DPI function with different names in C and Verilog
2014-08-21 17:22:04 +02:00
args.push_back(children.at(i-2)->clone());
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (args.back()->simplify(true, stage, -1, false)) { }
Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
2014-08-21 12:43:51 +02:00
if (args.back()->type != AST_CONSTANT && args.back()->type != AST_REALVALUE)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Failed to evaluate DPI function with non-constant argument.\n");
Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
2014-08-21 12:43:51 +02:00
}
neater errors, lost in the sauce of source
2025-06-18 18:05:48 +02:00
newNode = dpi_call(dpi_decl->location, rtype, fname, argtypes, args);
Fixed memory leak in DPI function calls
2014-08-21 13:09:47 +02:00
Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
2014-08-21 12:43:51 +02:00
goto apply_newNode;
}
verilog: Support module-scoped task/function calls This is primarily intended to enable the standard-permitted use of module-scoped identifiers to refer to tasks and non-constant functions. As a side-effect, this also adds support for the non-standard use of module-scoped identifiers referring to constant functions, a feature that is supported in some other tools, including Iverilog.
2022-10-29 21:14:11 +02:00
if (current_scope.count(str) == 0)
str = try_pop_module_prefix();
Added support for $clog2 system function
2013-12-04 21:19:54 +01:00
if (current_scope.count(str) == 0 || current_scope[str]->type != AST_FUNCTION)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Can't resolve function name `%s'.\n", str.c_str());
initial import
2013-01-05 11:13:26 +01:00
}
Added AST_INITIAL checks for $finish and $display
2015-09-18 09:50:53 +02:00
Initial implementation of $finish()
2015-09-18 05:34:56 +02:00
if (type == AST_TCALL)
{
Added support for $stop system task
2016-03-21 16:19:51 +01:00
if (str == "$finish" || str == "$stop")
Initial implementation of $finish()
2015-09-18 05:34:56 +02:00
{
Added AST_INITIAL checks for $finish and $display
2015-09-18 09:50:53 +02:00
if (!current_always || current_always->type != AST_INITIAL)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("System task `%s' outside initial block is unsupported.\n", str.c_str());
Added AST_INITIAL checks for $finish and $display
2015-09-18 09:50:53 +02:00
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("System task `%s' executed.\n", str.c_str());
Initial implementation of $finish()
2015-09-18 05:34:56 +02:00
}
Added support for $readmemh/$readmemb
2014-10-26 20:33:10 +01:00
if (str == "\\$readmemh" || str == "\\$readmemb")
{
if (GetSize(children) < 2 || GetSize(children) > 4)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("System function %s got %d arguments, expected 2-4.\n",
Various indenting fixes in AST front-end (mostly space vs tab issues) Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-04 10:19:32 +01:00
RTLIL::unescape_id(str).c_str(), int(children.size()));
Added support for $readmemh/$readmemb
2014-10-26 20:33:10 +01:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto node_filename = children[0]->clone();
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (node_filename->simplify(true, stage, width_hint, sign_hint)) { }
Added support for $readmemh/$readmemb
2014-10-26 20:33:10 +01:00
if (node_filename->type != AST_CONSTANT)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Failed to evaluate system function `%s' with non-constant 1st argument.\n", str.c_str());
Added support for $readmemh/$readmemb
2014-10-26 20:33:10 +01:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto node_memory = children[1]->clone();
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (node_memory->simplify(true, stage, width_hint, sign_hint)) { }
Added support for $readmemh/$readmemb
2014-10-26 20:33:10 +01:00
if (node_memory->type != AST_IDENTIFIER || node_memory->id2ast == nullptr || node_memory->id2ast->type != AST_MEMORY)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Failed to evaluate system function `%s' with non-memory 2nd argument.\n", str.c_str());
Added support for $readmemh/$readmemb
2014-10-26 20:33:10 +01:00
int start_addr = -1, finish_addr = -1;
if (GetSize(children) > 2) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto node_addr = children[2]->clone();
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (node_addr->simplify(true, stage, width_hint, sign_hint)) { }
Added support for $readmemh/$readmemb
2014-10-26 20:33:10 +01:00
if (node_addr->type != AST_CONSTANT)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Failed to evaluate system function `%s' with non-constant 3rd argument.\n", str.c_str());
Fixed some visual studio warnings
2016-02-13 17:31:24 +01:00
start_addr = int(node_addr->asInt(false));
Added support for $readmemh/$readmemb
2014-10-26 20:33:10 +01:00
}
if (GetSize(children) > 3) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto node_addr = children[3]->clone();
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (node_addr->simplify(true, stage, width_hint, sign_hint)) { }
Added support for $readmemh/$readmemb
2014-10-26 20:33:10 +01:00
if (node_addr->type != AST_CONSTANT)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Failed to evaluate system function `%s' with non-constant 4th argument.\n", str.c_str());
Fixed some visual studio warnings
2016-02-13 17:31:24 +01:00
finish_addr = int(node_addr->asInt(false));
Added support for $readmemh/$readmemb
2014-10-26 20:33:10 +01:00
}
Added WORDS parameter to $meminit
2015-07-31 10:40:09 +02:00
bool unconditional_init = false;
if (current_always->type == AST_INITIAL) {
Fixed detection of unconditional $readmem[hb]
2015-09-30 15:46:51 +02:00
pool<AstNode*> queue;
Added WORDS parameter to $meminit
2015-07-31 10:40:09 +02:00
log_assert(current_always->children[0]->type == AST_BLOCK);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
queue.insert(current_always->children[0].get());
Fixed detection of unconditional $readmem[hb]
2015-09-30 15:46:51 +02:00
while (!unconditional_init && !queue.empty()) {
pool<AstNode*> next_queue;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& n : queue)
for (auto& c : n->children) {
if (c.get() == this)
Fixed detection of unconditional $readmem[hb]
2015-09-30 15:46:51 +02:00
unconditional_init = true;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
next_queue.insert(c.get());
Added WORDS parameter to $meminit
2015-07-31 10:40:09 +02:00
}
Fixed detection of unconditional $readmem[hb]
2015-09-30 15:46:51 +02:00
next_queue.swap(queue);
}
Added WORDS parameter to $meminit
2015-07-31 10:40:09 +02:00
}
newNode = readmem(str == "\\$readmemh", node_filename->bitsAsConst().decode_string(), node_memory->id2ast, start_addr, finish_addr, unconditional_init);
Added support for $readmemh/$readmemb
2014-10-26 20:33:10 +01:00
goto apply_newNode;
}
verilog: Support module-scoped task/function calls This is primarily intended to enable the standard-permitted use of module-scoped identifiers to refer to tasks and non-constant functions. As a side-effect, this also adds support for the non-standard use of module-scoped identifiers referring to constant functions, a feature that is supported in some other tools, including Iverilog.
2022-10-29 21:14:11 +02:00
if (current_scope.count(str) == 0)
str = try_pop_module_prefix();
initial import
2013-01-05 11:13:26 +01:00
if (current_scope.count(str) == 0 || current_scope[str]->type != AST_TASK)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Can't resolve task name `%s'.\n", str.c_str());
initial import
2013-01-05 11:13:26 +01:00
}
Added "via_celltype" attribute on task/func
2014-08-18 14:29:30 +02:00
std::stringstream sstr;
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
sstr << str << "$func$" << RTLIL::encode_filename(*location.begin.filename) << ":" << location.begin.line << "$" << (autoidx++) << '.';
Added "via_celltype" attribute on task/func
2014-08-18 14:29:30 +02:00
std::string prefix = sstr.str();
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto* decl = current_scope[str];
verilog: support recursive functions using ternary expressions This adds a mechanism for marking certain portions of elaboration as occurring within unevaluated ternary branches. To enable elaboration of the overall ternary, this also adds width detection for these unelaborated function calls.
2021-02-12 20:25:34 +01:00
if (unevaluated_tern_branch && decl->is_recursive_function())
goto replace_fcall_later;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto decl_clone = decl->clone();
decl = decl_clone.get(); // sketchy?
verilog: significant block scoping improvements This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
2021-01-27 19:30:22 +01:00
decl->replace_result_wire_name_in_function(str, "$result"); // enables recursion
decl->expand_genblock(prefix);
verilog: refactored constant function evaluation Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
2021-01-27 19:21:13 +01:00
if (decl->type == AST_FUNCTION && !decl->attributes.count(ID::via_celltype))
Created basic support for function calls in parameter values
2014-02-14 19:56:44 +01:00
{
verilog: refactored constant function evaluation Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
2021-01-27 19:21:13 +01:00
bool require_const_eval = decl->has_const_only_constructs();
Created basic support for function calls in parameter values
2014-02-14 19:56:44 +01:00
bool all_args_const = true;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : children) {
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (child->simplify(true, 1, -1, false)) { }
Allow reals as constant function parameters
2020-07-20 04:27:09 +02:00
if (child->type != AST_CONSTANT && child->type != AST_REALVALUE)
Created basic support for function calls in parameter values
2014-02-14 19:56:44 +01:00
all_args_const = false;
Improved support for constant functions
2014-02-16 13:16:38 +01:00
}
Created basic support for function calls in parameter values
2014-02-14 19:56:44 +01:00
if (all_args_const) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto func_workspace = decl->clone();
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
func_workspace->set_in_param_flag(true);
verilog: significant block scoping improvements This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
2021-01-27 19:30:22 +01:00
func_workspace->str = prefix_id(prefix, "$result");
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
// func_workspace->dumpAst(stdout, "func_workspace ");
verilog: refactored constant function evaluation Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
2021-01-27 19:21:13 +01:00
newNode = func_workspace->eval_const_function(this, in_param || require_const_eval);
if (newNode) {
goto apply_newNode;
}
Created basic support for function calls in parameter values
2014-02-14 19:56:44 +01:00
}
improved const function support
2014-06-06 22:55:02 +02:00
if (in_param)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Non-constant function call in constant expression.\n");
further improved const function support
2014-06-07 00:02:05 +02:00
if (require_const_eval)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Function %s can only be called with constant arguments.\n", str.c_str());
Created basic support for function calls in parameter values
2014-02-14 19:56:44 +01:00
}
initial import
2013-01-05 11:13:26 +01:00
size_t arg_count = 0;
Fixed handling of re-declarations of wires in tasks and functions
2015-11-23 17:09:57 +01:00
dict<std::string, AstNode*> wire_cache;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
vector<std::unique_ptr<AstNode>> new_stmts;
vector<std::unique_ptr<AstNode>> output_assignments;
initial import
2013-01-05 11:13:26 +01:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
if (current_block == nullptr)
initial import
2013-01-05 11:13:26 +01:00
{
Using log_assert() instead of assert()
2014-07-28 11:08:55 +02:00
log_assert(type == AST_FCALL);
initial import
2013-01-05 11:13:26 +01:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
std::unique_ptr<AstNode> wire = nullptr;
verilog: significant block scoping improvements This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
2021-01-27 19:30:22 +01:00
std::string res_name = prefix_id(prefix, "$result");
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : decl->children)
verilog: significant block scoping improvements This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
2021-01-27 19:30:22 +01:00
if (child->type == AST_WIRE && child->str == res_name)
initial import
2013-01-05 11:13:26 +01:00
wire = child->clone();
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
log_assert(wire != nullptr);
initial import
2013-01-05 11:13:26 +01:00
wire->port_id = 0;
wire->is_input = false;
wire->is_output = false;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto* wire_leaky = wire.get();
current_scope[wire->str] = wire_leaky;
current_ast_mod->children.push_back(std::move(wire));
while (wire_leaky->simplify(true, 1, -1, false)) { }
initial import
2013-01-05 11:13:26 +01:00
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto lvalue = std::make_unique<AstNode>(location, AST_IDENTIFIER);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
lvalue->str = wire_leaky->str;
initial import
2013-01-05 11:13:26 +01:00
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto always = std::make_unique<AstNode>(location, AST_ALWAYS, std::make_unique<AstNode>(location, AST_BLOCK,
std::make_unique<AstNode>(location, AST_ASSIGN_EQ, std::move(lvalue), clone())));
Fixed remaining cases where we check fo wire reg/wire incorrect assignments on Yosys-generated assignments. In this case, offending code was: module top(input in, output out); function func; input arg; func = arg; endfunction assign out = func(in); endmodule
2018-09-18 00:23:40 +02:00
always->children[0]->children[0]->was_checked = true;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_ast_mod->children.push_back(std::move(always));
initial import
2013-01-05 11:13:26 +01:00
goto replace_fcall_with_id;
}
frontend: cleanup to use more ID::*, more dict<> instead of map<>
2020-05-04 19:48:37 +02:00
if (decl->attributes.count(ID::via_celltype))
Added "via_celltype" attribute on task/func
2014-08-18 14:29:30 +02:00
{
frontend: cleanup to use more ID::*, more dict<> instead of map<>
2020-05-04 19:48:37 +02:00
std::string celltype = decl->attributes.at(ID::via_celltype)->asAttrConst().decode_string();
Added "via_celltype" attribute on task/func
2014-08-18 14:29:30 +02:00
std::string outport = str;
if (celltype.find(' ') != std::string::npos) {
int pos = celltype.find(' ');
outport = RTLIL::escape_id(celltype.substr(pos+1));
celltype = RTLIL::escape_id(celltype.substr(0, pos));
} else
celltype = RTLIL::escape_id(celltype);
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto cell = std::make_unique<AstNode>(location, AST_CELL, std::make_unique<AstNode>(location, AST_CELLTYPE));
Renamed SIZE() to GetSize() because of name collision on Win32
2014-10-10 16:59:44 +02:00
cell->str = prefix.substr(0, GetSize(prefix)-1);
Added "via_celltype" attribute on task/func
2014-08-18 14:29:30 +02:00
cell->children[0]->str = celltype;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& attr : decl->attributes)
Added "via_celltype" attribute on task/func
2014-08-18 14:29:30 +02:00
if (attr.first.str().rfind("\\via_celltype_defparam_", 0) == 0)
{
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto cell_arg = std::make_unique<AstNode>(location, AST_PARASET, attr.second->clone());
IdString::str().substr() -> IdString::substr()
2019-08-07 04:08:33 +02:00
cell_arg->str = RTLIL::escape_id(attr.first.substr(strlen("\\via_celltype_defparam_")));
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
cell->children.push_back(std::move(cell_arg));
Added "via_celltype" attribute on task/func
2014-08-18 14:29:30 +02:00
}
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : decl->children)
Added "via_celltype" attribute on task/func
2014-08-18 14:29:30 +02:00
if (child->type == AST_WIRE && (child->is_input || child->is_output || (type == AST_FCALL && child->str == str)))
{
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto wire = child->clone();
Added "via_celltype" attribute on task/func
2014-08-18 14:29:30 +02:00
wire->port_id = 0;
wire->is_input = false;
wire->is_output = false;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_ast_mod->children.push_back(std::move(wire));
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (wire->simplify(true, 1, -1, false)) { }
Added "via_celltype" attribute on task/func
2014-08-18 14:29:30 +02:00
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto wire_id = std::make_unique<AstNode>(location, AST_IDENTIFIER);
Added "via_celltype" attribute on task/func
2014-08-18 14:29:30 +02:00
wire_id->str = wire->str;
if ((child->is_input || child->is_output) && arg_count < children.size())
{
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto arg = children[arg_count++]->clone();
auto assign = child->is_input ?
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
std::make_unique<AstNode>(location, AST_ASSIGN_EQ, wire_id->clone(), std::move(arg)) :
std::make_unique<AstNode>(location, AST_ASSIGN_EQ, std::move(arg), wire_id->clone());
Fixed remaining cases where we check fo wire reg/wire incorrect assignments on Yosys-generated assignments. In this case, offending code was: module top(input in, output out); function func; input arg; func = arg; endfunction assign out = func(in); endmodule
2018-09-18 00:23:40 +02:00
assign->children[0]->was_checked = true;
Added "via_celltype" attribute on task/func
2014-08-18 14:29:30 +02:00
for (auto it = current_block->children.begin(); it != current_block->children.end(); it++) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
if (it->get() != current_block_child)
Added "via_celltype" attribute on task/func
2014-08-18 14:29:30 +02:00
continue;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_block->children.insert(it, std::move(assign));
Added "via_celltype" attribute on task/func
2014-08-18 14:29:30 +02:00
break;
}
}
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto cell_arg = std::make_unique<AstNode>(location, AST_ARGUMENT, std::move(wire_id));
Added "via_celltype" attribute on task/func
2014-08-18 14:29:30 +02:00
cell_arg->str = child->str == str ? outport : child->str;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
cell->children.push_back(std::move(cell_arg));
Added "via_celltype" attribute on task/func
2014-08-18 14:29:30 +02:00
}
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_ast_mod->children.push_back(std::move(cell));
Added "via_celltype" attribute on task/func
2014-08-18 14:29:30 +02:00
goto replace_fcall_with_id;
}
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : decl->children)
partial rebase of PeterCrozier's enum work onto current master I tried to keep only the enum-related changes, and minimize the diff. (The original commit also had a lot of work done to get typedefs working, but yosys has diverged quite a bit since the 2018-03-09 commit, with a new typedef implementation.) I did not include the import related changes either. Original commit: "Initial implementation of enum, typedef, import. Still a WIP." https://github.com/PeterCrozier/yosys/commit/881833aa738e7404987646ea8076284e911fce3f
2018-03-09 13:47:11 +01:00
if (child->type == AST_WIRE || child->type == AST_MEMORY || child->type == AST_PARAMETER || child->type == AST_LOCALPARAM || child->type == AST_ENUM_ITEM)
initial import
2013-01-05 11:13:26 +01:00
{
Fixed handling of re-declarations of wires in tasks and functions
2015-11-23 17:09:57 +01:00
AstNode *wire = nullptr;
if (wire_cache.count(child->str))
{
wire = wire_cache.at(child->str);
Fix constant args used with function ports split across declarations
2020-08-29 19:31:02 +02:00
bool contains_value = wire->type == AST_LOCALPARAM;
if (wire->children.size() == contains_value) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& c : child->children)
Fixed handling of re-declarations of wires in tasks and functions
2015-11-23 17:09:57 +01:00
wire->children.push_back(c->clone());
Fix incorrect "incompatible re-declaration of wire" error in tasks/functions
2017-02-14 15:10:59 +01:00
} else if (!child->children.empty()) {
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (child->simplify(true, stage, -1, false)) { }
Fix constant args used with function ports split across declarations
2020-08-29 19:31:02 +02:00
if (GetSize(child->children) == GetSize(wire->children) - contains_value) {
Fix incorrect "incompatible re-declaration of wire" error in tasks/functions
2017-02-14 15:10:59 +01:00
for (int i = 0; i < GetSize(child->children); i++)
Fix constant args used with function ports split across declarations
2020-08-29 19:31:02 +02:00
if (*child->children.at(i) != *wire->children.at(i + contains_value))
Fix incorrect "incompatible re-declaration of wire" error in tasks/functions
2017-02-14 15:10:59 +01:00
goto tcall_incompatible_wires;
} else {
tcall_incompatible_wires:
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Incompatible re-declaration of wire %s.\n", child->str.c_str());
Fix incorrect "incompatible re-declaration of wire" error in tasks/functions
2017-02-14 15:10:59 +01:00
}
Fixed handling of re-declarations of wires in tasks and functions
2015-11-23 17:09:57 +01:00
}
}
else
{
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_ast_mod->children.push_back(child->clone());
wire = current_ast_mod->children.back().get();
Fixed handling of re-declarations of wires in tasks and functions
2015-11-23 17:09:57 +01:00
wire->port_id = 0;
wire->is_input = false;
wire->is_output = false;
Fix handling of task output ports in clocked always blocks, fixes #857 Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-08 07:44:37 +01:00
wire->is_reg = true;
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
wire->set_attribute(ID::nosync, AstNode::mkconst_int(location, 1, false));
remove unnecessary blank line
2020-02-17 10:40:02 +01:00
if (child->type == AST_ENUM_ITEM)
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
wire->set_attribute(ID::enum_base_type, std::move(child->attributes[ID::enum_base_type]));
add attributes for enumerated values in ilang - information also useful for strongly-typed enums (not implemented) - resolves enum values in ilang part of #1594 - still need to output enums to VCD (or better yet FST) files
2020-02-03 07:12:24 +01:00
Fixed handling of re-declarations of wires in tasks and functions
2015-11-23 17:09:57 +01:00
wire_cache[child->str] = wire;
verilog: significant block scoping improvements This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
2021-01-27 19:30:22 +01:00
current_scope[wire->str] = wire;
Fixed handling of re-declarations of wires in tasks and functions
2015-11-23 17:09:57 +01:00
}
More bugfixes in handling of parameters in tasks and functions
2015-11-12 13:02:36 +01:00
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (wire->simplify(true, 1, -1, false)) { }
initial import
2013-01-05 11:13:26 +01:00
Fixed handling of task outputs
2014-08-14 22:26:10 +02:00
if ((child->is_input || child->is_output) && arg_count < children.size())
initial import
2013-01-05 11:13:26 +01:00
{
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto arg = children[arg_count++]->clone();
Avoid generating wires for function args which are constant
2020-07-25 05:18:24 +02:00
// convert purely constant arguments into localparams
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
if (child->is_input && child->type == AST_WIRE && arg->type == AST_CONSTANT && node_contains_assignment_to(decl, child.get())) {
Avoid generating wires for function args which are constant
2020-07-25 05:18:24 +02:00
wire->type = AST_LOCALPARAM;
wire->attributes.erase(ID::nosync);
wire->children.insert(wire->children.begin(), arg->clone());
Fix constants bound to single bit arguments (fixes #2383)
2020-12-06 02:56:18 +01:00
// args without a range implicitly have width 1
if (wire->children.back()->type != AST_RANGE) {
Fix constants bound to redeclared function args The changes in #2476 ensured that function inputs like `input x;` retained their single-bit size when instantiated with a constant argument and turned into a localparam. That change did not handle the possibility for an input to be redeclared later on with an explicit width, such as `integer x;`.
2020-12-26 16:39:57 +01:00
// check if this wire is redeclared with an explicit size
bool uses_explicit_size = false;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& other_child : decl->children)
Fix constants bound to redeclared function args The changes in #2476 ensured that function inputs like `input x;` retained their single-bit size when instantiated with a constant argument and turned into a localparam. That change did not handle the possibility for an input to be redeclared later on with an explicit width, such as `integer x;`.
2020-12-26 16:39:57 +01:00
if (other_child->type == AST_WIRE && child->str == other_child->str
&& !other_child->children.empty()
&& other_child->children.back()->type == AST_RANGE) {
uses_explicit_size = true;
break;
}
if (!uses_explicit_size) {
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto range = std::make_unique<AstNode>(location);
Fix constants bound to redeclared function args The changes in #2476 ensured that function inputs like `input x;` retained their single-bit size when instantiated with a constant argument and turned into a localparam. That change did not handle the possibility for an input to be redeclared later on with an explicit width, such as `integer x;`.
2020-12-26 16:39:57 +01:00
range->type = AST_RANGE;
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
range->children.push_back(mkconst_int(location, 0, true));
range->children.push_back(mkconst_int(location, 0, true));
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
wire->children.push_back(std::move(range));
Fix constants bound to redeclared function args The changes in #2476 ensured that function inputs like `input x;` retained their single-bit size when instantiated with a constant argument and turned into a localparam. That change did not handle the possibility for an input to be redeclared later on with an explicit width, such as `integer x;`.
2020-12-26 16:39:57 +01:00
}
Fix constants bound to single bit arguments (fixes #2383)
2020-12-06 02:56:18 +01:00
}
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
wire->fixup_hierarchy_flags();
verilog: fix sizing of constant args for tasks/functions - Simplify synthetic localparams for normal calls to update their width - This step was inadvertently removed alongside `added_mod_children` - Support redeclaration of constant function arguments - `eval_const_function` never correctly handled this, but the issue was not exposed in the existing tests until the recent change to always attempt constant function evaluation when all-const args are used - Check asserts in const_arg_loop and const_func tests - Add coverage for width mismatch error cases
2021-02-21 20:45:21 +01:00
// updates the sizing
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (wire->simplify(true, 1, -1, false)) { }
Avoid generating wires for function args which are constant
2020-07-25 05:18:24 +02:00
continue;
}
read_verilog: copy inout ports in and out of functions/tasks
2025-05-31 02:08:15 +02:00
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto wire_id = std::make_unique<AstNode>(location, AST_IDENTIFIER);
initial import
2013-01-05 11:13:26 +01:00
wire_id->str = wire->str;
read_verilog: copy inout ports in and out of functions/tasks
2025-05-31 02:08:15 +02:00
if (child->is_input) {
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto assign = std::make_unique<AstNode>(location, AST_ASSIGN_EQ, wire_id->clone(), arg->clone());
read_verilog: copy inout ports in and out of functions/tasks
2025-05-31 02:08:15 +02:00
assign->children[0]->was_checked = true;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
new_stmts.push_back(std::move(assign));
read_verilog: copy inout ports in and out of functions/tasks
2025-05-31 02:08:15 +02:00
}
if (child->is_output) {
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto assign = std::make_unique<AstNode>(location, AST_ASSIGN_EQ, arg->clone(), wire_id->clone());
read_verilog: copy inout ports in and out of functions/tasks
2025-05-31 02:08:15 +02:00
assign->children[0]->was_checked = true;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
output_assignments.push_back(std::move(assign));
read_verilog: copy inout ports in and out of functions/tasks
2025-05-31 02:08:15 +02:00
}
initial import
2013-01-05 11:13:26 +01:00
}
}
Fixed AST handling of variables declared inside a functions main block
2014-08-05 08:35:51 +02:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : decl->children)
Fixed handling of local memories in functions
2017-01-05 13:18:58 +01:00
if (child->type != AST_WIRE && child->type != AST_MEMORY && child->type != AST_PARAMETER && child->type != AST_LOCALPARAM)
verilog: significant block scoping improvements This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
2021-01-27 19:30:22 +01:00
new_stmts.push_back(child->clone());
initial import
2013-01-05 11:13:26 +01:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
new_stmts.reserve(new_stmts.size() + output_assignments.size());
std::move(output_assignments.begin(), output_assignments.end(), std::back_inserter(new_stmts));
Fix handling of task output ports in clocked always blocks, fixes #857 Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-08 07:44:37 +01:00
for (auto it = current_block->children.begin(); ; it++) {
log_assert(it != current_block->children.end());
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
if (it->get() == current_block_child) {
current_block->children.insert(it,
std::make_move_iterator(new_stmts.begin()),
std::make_move_iterator(new_stmts.end()));
Fix handling of task output ports in clocked always blocks, fixes #857 Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-08 07:44:37 +01:00
break;
initial import
2013-01-05 11:13:26 +01:00
}
Fix handling of task output ports in clocked always blocks, fixes #857 Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-08 07:44:37 +01:00
}
initial import
2013-01-05 11:13:26 +01:00
replace_fcall_with_id:
if (type == AST_FCALL) {
delete_children();
type = AST_IDENTIFIER;
verilog: significant block scoping improvements This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
2021-01-27 19:30:22 +01:00
str = prefix_id(prefix, "$result");
initial import
2013-01-05 11:13:26 +01:00
}
if (type == AST_TCALL)
str = "";
did_something = true;
}
Added $past, $stable, $rose, $fell SVA functions
2016-09-19 01:30:07 +02:00
replace_fcall_later:;
initial import
2013-01-05 11:13:26 +01:00
// perform const folding when activated
Added const folding of AST_CASE to AST simplifier
2014-08-18 00:02:30 +02:00
if (const_fold)
initial import
2013-01-05 11:13:26 +01:00
{
Keep strings as strings in const ternary and concat
2013-12-05 13:26:17 +01:00
bool string_op;
Fixes and improvements in AST const folding
2013-06-10 13:56:03 +02:00
std::vector<RTLIL::State> tmp_bits;
initial import
2013-01-05 11:13:26 +01:00
RTLIL::Const (*const_func)(const RTLIL::Const&, const RTLIL::Const&, bool, bool, int);
RTLIL::Const dummy_arg;
switch (type)
{
case AST_IDENTIFIER:
partial rebase of PeterCrozier's enum work onto current master I tried to keep only the enum-related changes, and minimize the diff. (The original commit also had a lot of work done to get typedefs working, but yosys has diverged quite a bit since the 2018-03-09 commit, with a new typedef implementation.) I did not include the import related changes either. Original commit: "Initial implementation of enum, typedef, import. Still a WIP." https://github.com/PeterCrozier/yosys/commit/881833aa738e7404987646ea8076284e911fce3f
2018-03-09 13:47:11 +01:00
if (current_scope.count(str) > 0 && (current_scope[str]->type == AST_PARAMETER || current_scope[str]->type == AST_LOCALPARAM || current_scope[str]->type == AST_ENUM_ITEM)) {
Fixed const folding in corner cases with parameters
2013-11-07 14:08:53 +01:00
if (current_scope[str]->children[0]->type == AST_CONSTANT) {
if (children.size() != 0 && children[0]->type == AST_RANGE && children[0]->range_valid) {
initial import
2013-01-05 11:13:26 +01:00
std::vector<RTLIL::State> data;
Fixed part selects of parameters
2014-07-28 16:45:26 +02:00
bool param_upto = current_scope[str]->range_valid && current_scope[str]->range_swapped;
int param_offset = current_scope[str]->range_valid ? current_scope[str]->range_right : 0;
int param_width = current_scope[str]->range_valid ? current_scope[str]->range_left - current_scope[str]->range_right + 1 :
Renamed SIZE() to GetSize() because of name collision on Win32
2014-10-10 16:59:44 +02:00
GetSize(current_scope[str]->children[0]->bits);
Fixed part selects of parameters
2014-07-28 16:45:26 +02:00
int tmp_range_left = children[0]->range_left, tmp_range_right = children[0]->range_right;
if (param_upto) {
tmp_range_left = (param_width + 2*param_offset) - children[0]->range_right - 1;
tmp_range_right = (param_width + 2*param_offset) - children[0]->range_left - 1;
}
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
AstNode *member_node = get_struct_member();
Index struct/union members within corresponding wire chunks This guards against access to bits outside of struct/union members via dynamic indexing.
2023-02-28 18:45:55 +01:00
int chunk_offset = member_node ? member_node->range_right : 0;
log_assert(!(chunk_offset && param_upto));
Fixed part selects of parameters
2014-07-28 16:45:26 +02:00
for (int i = tmp_range_right; i <= tmp_range_left; i++) {
int index = i - param_offset;
if (0 <= index && index < param_width)
Index struct/union members within corresponding wire chunks This guards against access to bits outside of struct/union members via dynamic indexing.
2023-02-28 18:45:55 +01:00
data.push_back(current_scope[str]->children[0]->bits[chunk_offset + index]);
Fixed part selects of parameters
2014-07-28 16:45:26 +02:00
else
data.push_back(RTLIL::State::Sx);
}
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = mkconst_bits(location, data, false);
Fixed const folding in corner cases with parameters
2013-11-07 14:08:53 +01:00
} else
if (children.size() == 0)
newNode = current_scope[str]->children[0]->clone();
Implemented more real arithmetic
2014-06-14 11:27:05 +02:00
} else
if (current_scope[str]->children[0]->isConst())
newNode = current_scope[str]->children[0]->clone();
initial import
2013-01-05 11:13:26 +01:00
}
break;
case AST_BIT_NOT:
if (children[0]->type == AST_CONSTANT) {
Use proper bit width ans sign extension for const folding
2013-11-04 15:37:09 +01:00
RTLIL::Const y = RTLIL::const_not(children[0]->bitsAsConst(width_hint, sign_hint), dummy_arg, sign_hint, false, width_hint);
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = mkconst_bits(location, y.to_bits(), sign_hint);
initial import
2013-01-05 11:13:26 +01:00
}
break;
Added const folding support for $signed and $unsigned
2013-12-05 13:09:41 +01:00
case AST_TO_SIGNED:
case AST_TO_UNSIGNED:
if (children[0]->type == AST_CONSTANT) {
RTLIL::Const y = children[0]->bitsAsConst(width_hint, sign_hint);
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = mkconst_bits(location, y.to_bits(), type == AST_TO_SIGNED);
Added const folding support for $signed and $unsigned
2013-12-05 13:09:41 +01:00
}
break;
initial import
2013-01-05 11:13:26 +01:00
if (0) { case AST_BIT_AND: const_func = RTLIL::const_and; }
if (0) { case AST_BIT_OR: const_func = RTLIL::const_or; }
if (0) { case AST_BIT_XOR: const_func = RTLIL::const_xor; }
if (0) { case AST_BIT_XNOR: const_func = RTLIL::const_xnor; }
if (children[0]->type == AST_CONSTANT && children[1]->type == AST_CONSTANT) {
Use proper bit width ans sign extension for const folding
2013-11-04 15:37:09 +01:00
RTLIL::Const y = const_func(children[0]->bitsAsConst(width_hint, sign_hint),
children[1]->bitsAsConst(width_hint, sign_hint), sign_hint, sign_hint, width_hint);
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = mkconst_bits(location, y.to_bits(), sign_hint);
initial import
2013-01-05 11:13:26 +01:00
}
break;
if (0) { case AST_REDUCE_AND: const_func = RTLIL::const_reduce_and; }
if (0) { case AST_REDUCE_OR: const_func = RTLIL::const_reduce_or; }
if (0) { case AST_REDUCE_XOR: const_func = RTLIL::const_reduce_xor; }
if (0) { case AST_REDUCE_XNOR: const_func = RTLIL::const_reduce_xnor; }
if (0) { case AST_REDUCE_BOOL: const_func = RTLIL::const_reduce_bool; }
Enabled AST/Verilog front-end optimizations per default
2013-06-10 13:19:04 +02:00
if (children[0]->type == AST_CONSTANT) {
Use proper bit width ans sign extension for const folding
2013-11-04 15:37:09 +01:00
RTLIL::Const y = const_func(RTLIL::Const(children[0]->bits), dummy_arg, false, false, -1);
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = mkconst_bits(location, y.to_bits(), false);
initial import
2013-01-05 11:13:26 +01:00
}
break;
case AST_LOGIC_NOT:
if (children[0]->type == AST_CONSTANT) {
RTLIL::Const y = RTLIL::const_logic_not(RTLIL::Const(children[0]->bits), dummy_arg, children[0]->is_signed, false, -1);
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = mkconst_bits(location, y.to_bits(), false);
Implemented more real arithmetic
2014-06-14 11:27:05 +02:00
} else
if (children[0]->isConst()) {
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = mkconst_int(location, children[0]->asReal(sign_hint) == 0, false, 1);
initial import
2013-01-05 11:13:26 +01:00
}
break;
if (0) { case AST_LOGIC_AND: const_func = RTLIL::const_logic_and; }
if (0) { case AST_LOGIC_OR: const_func = RTLIL::const_logic_or; }
if (children[0]->type == AST_CONSTANT && children[1]->type == AST_CONSTANT) {
RTLIL::Const y = const_func(RTLIL::Const(children[0]->bits), RTLIL::Const(children[1]->bits),
children[0]->is_signed, children[1]->is_signed, -1);
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = mkconst_bits(location, y.to_bits(), false);
Implemented more real arithmetic
2014-06-14 11:27:05 +02:00
} else
if (children[0]->isConst() && children[1]->isConst()) {
if (type == AST_LOGIC_AND)
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = mkconst_int(location, (children[0]->asReal(sign_hint) != 0) && (children[1]->asReal(sign_hint) != 0), false, 1);
Implemented more real arithmetic
2014-06-14 11:27:05 +02:00
else
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = mkconst_int(location, (children[0]->asReal(sign_hint) != 0) || (children[1]->asReal(sign_hint) != 0), false, 1);
initial import
2013-01-05 11:13:26 +01:00
}
break;
if (0) { case AST_SHIFT_LEFT: const_func = RTLIL::const_shl; }
if (0) { case AST_SHIFT_RIGHT: const_func = RTLIL::const_shr; }
if (0) { case AST_SHIFT_SLEFT: const_func = RTLIL::const_sshl; }
if (0) { case AST_SHIFT_SRIGHT: const_func = RTLIL::const_sshr; }
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
if (0) { case AST_POW: const_func = RTLIL::const_pow; }
initial import
2013-01-05 11:13:26 +01:00
if (children[0]->type == AST_CONSTANT && children[1]->type == AST_CONSTANT) {
Use proper bit width ans sign extension for const folding
2013-11-04 15:37:09 +01:00
RTLIL::Const y = const_func(children[0]->bitsAsConst(width_hint, sign_hint),
Fixed handling of different signedness in power operands
2013-11-08 11:06:11 +01:00
RTLIL::Const(children[1]->bits), sign_hint, type == AST_POW ? children[1]->is_signed : false, width_hint);
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = mkconst_bits(location, y.to_bits(), sign_hint);
Implemented more real arithmetic
2014-06-14 11:27:05 +02:00
} else
if (type == AST_POW && children[0]->isConst() && children[1]->isConst()) {
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = std::make_unique<AstNode>(location, AST_REALVALUE);
Implemented more real arithmetic
2014-06-14 11:27:05 +02:00
newNode->realvalue = pow(children[0]->asReal(sign_hint), children[1]->asReal(sign_hint));
initial import
2013-01-05 11:13:26 +01:00
}
break;
Added proper === and !== support in constant expressions
2013-12-27 13:50:08 +01:00
if (0) { case AST_LT: const_func = RTLIL::const_lt; }
if (0) { case AST_LE: const_func = RTLIL::const_le; }
if (0) { case AST_EQ: const_func = RTLIL::const_eq; }
if (0) { case AST_NE: const_func = RTLIL::const_ne; }
if (0) { case AST_EQX: const_func = RTLIL::const_eqx; }
if (0) { case AST_NEX: const_func = RTLIL::const_nex; }
if (0) { case AST_GE: const_func = RTLIL::const_ge; }
if (0) { case AST_GT: const_func = RTLIL::const_gt; }
initial import
2013-01-05 11:13:26 +01:00
if (children[0]->type == AST_CONSTANT && children[1]->type == AST_CONSTANT) {
Import more std:: stuff into Yosys namespace
2015-10-25 19:30:49 +01:00
int cmp_width = max(children[0]->bits.size(), children[1]->bits.size());
Use proper bit width ans sign extension for const folding
2013-11-04 15:37:09 +01:00
bool cmp_signed = children[0]->is_signed && children[1]->is_signed;
RTLIL::Const y = const_func(children[0]->bitsAsConst(cmp_width, cmp_signed),
children[1]->bitsAsConst(cmp_width, cmp_signed), cmp_signed, cmp_signed, 1);
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = mkconst_bits(location, y.to_bits(), false);
Implemented more real arithmetic
2014-06-14 11:27:05 +02:00
} else
if (children[0]->isConst() && children[1]->isConst()) {
Improved handling of relational op of real values
2014-06-17 12:47:51 +02:00
bool cmp_signed = (children[0]->type == AST_REALVALUE || children[0]->is_signed) && (children[1]->type == AST_REALVALUE || children[1]->is_signed);
Implemented more real arithmetic
2014-06-14 11:27:05 +02:00
switch (type) {
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
case AST_LT: newNode = mkconst_int(location, children[0]->asReal(cmp_signed) < children[1]->asReal(cmp_signed), false, 1); break;
case AST_LE: newNode = mkconst_int(location, children[0]->asReal(cmp_signed) <= children[1]->asReal(cmp_signed), false, 1); break;
case AST_EQ: newNode = mkconst_int(location, children[0]->asReal(cmp_signed) == children[1]->asReal(cmp_signed), false, 1); break;
case AST_NE: newNode = mkconst_int(location, children[0]->asReal(cmp_signed) != children[1]->asReal(cmp_signed), false, 1); break;
case AST_EQX: newNode = mkconst_int(location, children[0]->asReal(cmp_signed) == children[1]->asReal(cmp_signed), false, 1); break;
case AST_NEX: newNode = mkconst_int(location, children[0]->asReal(cmp_signed) != children[1]->asReal(cmp_signed), false, 1); break;
case AST_GE: newNode = mkconst_int(location, children[0]->asReal(cmp_signed) >= children[1]->asReal(cmp_signed), false, 1); break;
case AST_GT: newNode = mkconst_int(location, children[0]->asReal(cmp_signed) > children[1]->asReal(cmp_signed), false, 1); break;
Implemented more real arithmetic
2014-06-14 11:27:05 +02:00
default: log_abort();
}
initial import
2013-01-05 11:13:26 +01:00
}
break;
if (0) { case AST_ADD: const_func = RTLIL::const_add; }
if (0) { case AST_SUB: const_func = RTLIL::const_sub; }
if (0) { case AST_MUL: const_func = RTLIL::const_mul; }
if (0) { case AST_DIV: const_func = RTLIL::const_div; }
if (0) { case AST_MOD: const_func = RTLIL::const_mod; }
Implemented more real arithmetic
2014-06-14 11:27:05 +02:00
if (children[0]->type == AST_CONSTANT && children[1]->type == AST_CONSTANT) {
RTLIL::Const y = const_func(children[0]->bitsAsConst(width_hint, sign_hint),
children[1]->bitsAsConst(width_hint, sign_hint), sign_hint, sign_hint, width_hint);
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = mkconst_bits(location, y.to_bits(), sign_hint);
Implemented more real arithmetic
2014-06-14 11:27:05 +02:00
} else
Implemented basic real arithmetic
2014-06-14 08:51:22 +02:00
if (children[0]->isConst() && children[1]->isConst()) {
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = std::make_unique<AstNode>(location, AST_REALVALUE);
Implemented more real arithmetic
2014-06-14 11:27:05 +02:00
switch (type) {
case AST_ADD: newNode->realvalue = children[0]->asReal(sign_hint) + children[1]->asReal(sign_hint); break;
case AST_SUB: newNode->realvalue = children[0]->asReal(sign_hint) - children[1]->asReal(sign_hint); break;
case AST_MUL: newNode->realvalue = children[0]->asReal(sign_hint) * children[1]->asReal(sign_hint); break;
case AST_DIV: newNode->realvalue = children[0]->asReal(sign_hint) / children[1]->asReal(sign_hint); break;
case AST_MOD: newNode->realvalue = fmod(children[0]->asReal(sign_hint), children[1]->asReal(sign_hint)); break;
default: log_abort();
Implemented basic real arithmetic
2014-06-14 08:51:22 +02:00
}
initial import
2013-01-05 11:13:26 +01:00
}
break;
Add AST_SELFSZ and improve handling of bit slices Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-29 14:28:04 +02:00
if (0) { case AST_SELFSZ: const_func = RTLIL::const_pos; }
initial import
2013-01-05 11:13:26 +01:00
if (0) { case AST_POS: const_func = RTLIL::const_pos; }
if (0) { case AST_NEG: const_func = RTLIL::const_neg; }
if (children[0]->type == AST_CONSTANT) {
Use proper bit width ans sign extension for const folding
2013-11-04 15:37:09 +01:00
RTLIL::Const y = const_func(children[0]->bitsAsConst(width_hint, sign_hint), dummy_arg, sign_hint, false, width_hint);
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = mkconst_bits(location, y.to_bits(), sign_hint);
Implemented more real arithmetic
2014-06-14 11:27:05 +02:00
} else
if (children[0]->isConst()) {
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = std::make_unique<AstNode>(location, AST_REALVALUE);
Add AST_SELFSZ and improve handling of bit slices Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-29 14:28:04 +02:00
if (type == AST_NEG)
Implemented more real arithmetic
2014-06-14 11:27:05 +02:00
newNode->realvalue = -children[0]->asReal(sign_hint);
Add AST_SELFSZ and improve handling of bit slices Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-29 14:28:04 +02:00
else
newNode->realvalue = +children[0]->asReal(sign_hint);
initial import
2013-01-05 11:13:26 +01:00
}
break;
case AST_TERNARY:
Improved ternary support for real values
2014-06-16 15:12:24 +02:00
if (children[0]->isConst())
{
verilog: support recursive functions using ternary expressions This adds a mechanism for marking certain portions of elaboration as occurring within unevaluated ternary branches. To enable elaboration of the overall ternary, this also adds width detection for these unelaborated function calls.
2021-02-12 20:25:34 +01:00
auto pair = get_tern_choice();
AstNode *choice = pair.first;
AstNode *not_choice = pair.second;
Improved ternary support for real values
2014-06-16 15:12:24 +02:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
if (choice != nullptr) {
Implemented more real arithmetic
2014-06-14 11:27:05 +02:00
if (choice->type == AST_CONSTANT) {
Improved ternary support for real values
2014-06-16 15:12:24 +02:00
int other_width_hint = width_hint;
bool other_sign_hint = sign_hint, other_real = false;
not_choice->detectSignWidth(other_width_hint, other_sign_hint, &other_real);
if (other_real) {
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = std::make_unique<AstNode>(location, AST_REALVALUE);
Fixed handling of mixed real/int ternary expressions
2014-06-25 10:05:36 +02:00
choice->detectSignWidth(width_hint, sign_hint);
Improved ternary support for real values
2014-06-16 15:12:24 +02:00
newNode->realvalue = choice->asReal(sign_hint);
} else {
RTLIL::Const y = choice->bitsAsConst(width_hint, sign_hint);
rtlil: represent Const strings as std::string
2024-10-09 19:39:45 +02:00
if (choice->is_string && y.size() % 8 == 0 && sign_hint == false)
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = mkconst_str(location, y.to_bits());
Improved ternary support for real values
2014-06-16 15:12:24 +02:00
else
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = mkconst_bits(location, y.to_bits(), sign_hint);
Improved ternary support for real values
2014-06-16 15:12:24 +02:00
}
Implemented more real arithmetic
2014-06-14 11:27:05 +02:00
} else
if (choice->isConst()) {
newNode = choice->clone();
}
Implemented const folding of ternary op with undef select
2013-11-08 04:44:09 +01:00
} else if (children[1]->type == AST_CONSTANT && children[2]->type == AST_CONSTANT) {
RTLIL::Const a = children[1]->bitsAsConst(width_hint, sign_hint);
RTLIL::Const b = children[2]->bitsAsConst(width_hint, sign_hint);
rtlil: represent Const strings as std::string
2024-10-09 19:39:45 +02:00
log_assert(a.size() == b.size());
Reduce comparisons of size_t and int `Const::size()` returns int, so change iterators that use it to `auto` instead of `size_t`. For cases where size is being explicitly cast to `int`, use the wrapper that we already have instead: `Yosys::GetSize()`.
2024-11-29 00:31:34 +01:00
for (auto i = 0; i < a.size(); i++)
rtlil: represent Const strings as std::string
2024-10-09 19:39:45 +02:00
if (a[i] != b[i])
a.bits()[i] = RTLIL::State::Sx;
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = mkconst_bits(location, a.to_bits(), sign_hint);
Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012
2014-06-16 15:05:37 +02:00
} else if (children[1]->isConst() && children[2]->isConst()) {
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = std::make_unique<AstNode>(location, AST_REALVALUE);
Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012
2014-06-16 15:05:37 +02:00
if (children[1]->asReal(sign_hint) == children[2]->asReal(sign_hint))
newNode->realvalue = children[1]->asReal(sign_hint);
else
// IEEE Std 1800-2012 Sec. 11.4.11 states that the entry in Table 7-1 for
// the data type in question should be returned if the ?: is ambiguous. The
// value in Table 7-1 for the 'real' type is 0.0.
newNode->realvalue = 0.0;
Fixed const folding of ternary operator
2013-11-04 16:46:14 +01:00
}
initial import
2013-01-05 11:13:26 +01:00
}
break;
static cast: simplify
2020-06-20 04:09:43 +02:00
case AST_CAST_SIZE:
if (children.at(0)->type == AST_CONSTANT && children.at(1)->type == AST_CONSTANT) {
int width = children[0]->bitsAsConst().as_int();
sv: fix some edge cases for unbased unsized literals - Fix explicit size cast of unbased unsized literals - Fix unbased unsized literal bound directly to port - Output `is_unsized` flag in `dumpAst`
2021-03-03 20:36:19 +01:00
RTLIL::Const val;
if (children[1]->is_unsized)
val = children[1]->bitsAsUnsizedConst(width);
else
val = children[1]->bitsAsConst(width);
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = mkconst_bits(location, val.to_bits(), children[1]->is_signed);
static cast: simplify
2020-06-20 04:09:43 +02:00
}
break;
Fixes and improvements in AST const folding
2013-06-10 13:56:03 +02:00
case AST_CONCAT:
Keep strings as strings in const ternary and concat
2013-12-05 13:26:17 +01:00
string_op = !children.empty();
Fixes and improvements in AST const folding
2013-06-10 13:56:03 +02:00
for (auto it = children.begin(); it != children.end(); it++) {
if ((*it)->type != AST_CONSTANT)
goto not_const;
Keep strings as strings in const ternary and concat
2013-12-05 13:26:17 +01:00
if (!(*it)->is_string)
string_op = false;
Fixes and improvements in AST const folding
2013-06-10 13:56:03 +02:00
tmp_bits.insert(tmp_bits.end(), (*it)->bits.begin(), (*it)->bits.end());
}
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = string_op ? mkconst_str(location, tmp_bits) : mkconst_bits(location, tmp_bits, false);
Fixed const folding in corner cases with parameters
2013-11-07 14:08:53 +01:00
break;
case AST_REPLICATE:
if (children.at(0)->type != AST_CONSTANT || children.at(1)->type != AST_CONSTANT)
goto not_const;
for (int i = 0; i < children[0]->bitsAsConst().as_int(); i++)
tmp_bits.insert(tmp_bits.end(), children.at(1)->bits.begin(), children.at(1)->bits.end());
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = children.at(1)->is_string ? mkconst_str(location, tmp_bits) : mkconst_bits(location, tmp_bits, false);
Fixes and improvements in AST const folding
2013-06-10 13:56:03 +02:00
break;
initial import
2013-01-05 11:13:26 +01:00
default:
Fixes and improvements in AST const folding
2013-06-10 13:56:03 +02:00
not_const:
initial import
2013-01-05 11:13:26 +01:00
break;
}
}
// if any of the above set 'newNode' -> use 'newNode' as template to update 'this'
if (newNode) {
apply_newNode:
// fprintf(stderr, "----\n");
// dumpAst(stderr, "- ");
// newNode->dumpAst(stderr, "+ ");
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
log_assert(newNode != nullptr);
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode->location.begin.filename = location.begin.filename;
Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
2020-02-23 08:19:52 +01:00
newNode->location = location;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
newNode->cloneInto(*this);
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
fixup_hierarchy_flags();
initial import
2013-01-05 11:13:26 +01:00
did_something = true;
}
Fixed algorithmic complexity of AST simplification of long expressions
2014-01-20 20:25:20 +01:00
if (!did_something)
basic_prep = true;
Added AstNode::simplify() recursion counter
2015-02-13 12:33:12 +01:00
recursion_counter--;
initial import
2013-01-05 11:13:26 +01:00
return did_something;
}
verilog: improved support for recursive functions
2021-01-01 01:23:36 +01:00
void AstNode::replace_result_wire_name_in_function(const std::string &from, const std::string &to)
Fixed name resolution of local tasks and functions in generate block
2013-11-20 11:05:58 +01:00
{
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : children)
verilog: improved support for recursive functions
2021-01-01 01:23:36 +01:00
child->replace_result_wire_name_in_function(from, to);
if (str == from && type != AST_FCALL && type != AST_TCALL)
str = to;
Fixed name resolution of local tasks and functions in generate block
2013-11-20 11:05:58 +01:00
}
Added support for $readmemh/$readmemb
2014-10-26 20:33:10 +01:00
// replace a readmem[bh] TCALL ast node with a block of memory assignments
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
std::unique_ptr<AstNode> AstNode::readmem(bool is_readmemh, std::string mem_filename, AstNode *memory, int start_addr, int finish_addr, bool unconditional_init)
Added support for $readmemh/$readmemb
2014-10-26 20:33:10 +01:00
{
Bugfixes in $readmem[hb]
2015-09-25 13:49:48 +02:00
int mem_width, mem_size, addr_bits;
memory->meminfo(mem_width, mem_size, addr_bits);
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto block = std::make_unique<AstNode>(location, AST_BLOCK);
Added support for $readmemh/$readmemb
2014-10-26 20:33:10 +01:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
AstNode* meminit = nullptr;
Keep gcc from complaining about uninitialized variables
2015-08-14 22:22:17 +02:00
int next_meminit_cursor=0;
Added WORDS parameter to $meminit
2015-07-31 10:40:09 +02:00
vector<State> meminit_bits;
verilog: Emit $meminit_v2 cell. Fixes #2447.
2021-05-21 02:27:06 +02:00
vector<State> en_bits;
Keep gcc from complaining about uninitialized variables
2015-08-14 22:22:17 +02:00
int meminit_size=0;
Added WORDS parameter to $meminit
2015-07-31 10:40:09 +02:00
verilog: Emit $meminit_v2 cell. Fixes #2447.
2021-05-21 02:27:06 +02:00
for (int i = 0; i < mem_width; i++)
en_bits.push_back(State::S1);
Added support for $readmemh/$readmemb
2014-10-26 20:33:10 +01:00
std::ifstream f;
Modified the new search for files of $readmem[hb] to be backward compatible Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
2020-02-01 02:10:51 +01:00
f.open(mem_filename.c_str());
if (f.fail()) {
Modified $readmem[hb] to use '\' or '/' according the OS Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
2020-02-06 14:10:29 +01:00
#ifdef _WIN32
char slash = '\\';
#else
char slash = '/';
#endif
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
std::string path = location.begin.filename->substr(0, location.begin.filename->find_last_of(slash)+1);
Modified the new search for files of $readmem[hb] to be backward compatible Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
2020-02-01 02:10:51 +01:00
f.open(path + mem_filename.c_str());
yosys_input_files.insert(path + mem_filename);
} else {
yosys_input_files.insert(mem_filename);
}
Replaced strlen by GetSize into simplify.cc As recommended in CodingReadme. Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
2020-02-03 14:30:33 +01:00
if (f.fail() || GetSize(mem_filename) == 0)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Can not open file `%s` for %s.\n", mem_filename.c_str(), str.c_str());
Added support for $readmemh/$readmemb
2014-10-26 20:33:10 +01:00
Improvements in $readmem[bh] implementation
2014-10-26 23:29:36 +01:00
log_assert(GetSize(memory->children) == 2 && memory->children[1]->type == AST_RANGE && memory->children[1]->range_valid);
int range_left = memory->children[1]->range_left, range_right = memory->children[1]->range_right;
Import more std:: stuff into Yosys namespace
2015-10-25 19:30:49 +01:00
int range_min = min(range_left, range_right), range_max = max(range_left, range_right);
Improvements in $readmem[bh] implementation
2014-10-26 23:29:36 +01:00
if (start_addr < 0)
start_addr = range_min;
if (finish_addr < 0)
Bugfixes in $readmem[hb]
2015-09-25 13:49:48 +02:00
finish_addr = range_max + 1;
Added support for $readmemh/$readmemb
2014-10-26 20:33:10 +01:00
bool in_comment = false;
Improvements in $readmem[bh] implementation
2014-10-26 23:29:36 +01:00
int increment = start_addr <= finish_addr ? +1 : -1;
int cursor = start_addr;
Added support for $readmemh/$readmemb
2014-10-26 20:33:10 +01:00
while (!f.eof())
{
std::string line, token;
std::getline(f, line);
for (int i = 0; i < GetSize(line); i++) {
substr() -> compare()
2019-08-07 21:20:08 +02:00
if (in_comment && line.compare(i, 2, "*/") == 0) {
Added support for $readmemh/$readmemb
2014-10-26 20:33:10 +01:00
line[i] = ' ';
line[i+1] = ' ';
in_comment = false;
continue;
}
substr() -> compare()
2019-08-07 21:20:08 +02:00
if (!in_comment && line.compare(i, 2, "/*") == 0)
Added support for $readmemh/$readmemb
2014-10-26 20:33:10 +01:00
in_comment = true;
if (in_comment)
line[i] = ' ';
}
while (1)
{
token = next_token(line, " \t\r\n");
substr() -> compare()
2019-08-07 21:20:08 +02:00
if (token.empty() || token.compare(0, 2, "//") == 0)
Added support for $readmemh/$readmemb
2014-10-26 20:33:10 +01:00
break;
if (token[0] == '@') {
token = token.substr(1);
const char *nptr = token.c_str();
char *endptr;
cursor = strtol(nptr, &endptr, 16);
if (!*nptr || *endptr)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Can not parse address `%s` for %s.\n", nptr, str.c_str());
Added support for $readmemh/$readmemb
2014-10-26 20:33:10 +01:00
continue;
}
neater errors, lost in the sauce of source
2025-06-18 18:05:48 +02:00
VERILOG_FRONTEND::ConstParser p{memory->location};
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto value = p.const2ast(stringf("%d'%c", mem_width, is_readmemh ? 'h' : 'b') + token);
Added support for $readmemh/$readmemb
2014-10-26 20:33:10 +01:00
Added WORDS parameter to $meminit
2015-07-31 10:40:09 +02:00
if (unconditional_init)
{
if (meminit == nullptr || cursor != next_meminit_cursor)
{
if (meminit != nullptr) {
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
meminit->children[1] = AstNode::mkconst_bits(location, meminit_bits, false);
meminit->children[3] = AstNode::mkconst_int(location, meminit_size, false);
Added WORDS parameter to $meminit
2015-07-31 10:40:09 +02:00
}
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto meminit_owned = std::make_unique<AstNode>(location, AST_MEMINIT);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
meminit = meminit_owned.get();
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
meminit->children.push_back(AstNode::mkconst_int(location, cursor, false));
Added WORDS parameter to $meminit
2015-07-31 10:40:09 +02:00
meminit->children.push_back(nullptr);
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
meminit->children.push_back(AstNode::mkconst_bits(location, en_bits, false));
Added WORDS parameter to $meminit
2015-07-31 10:40:09 +02:00
meminit->children.push_back(nullptr);
meminit->str = memory->str;
meminit->id2ast = memory;
meminit_bits.clear();
meminit_size = 0;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_ast_mod->children.push_back(std::move(meminit_owned));
Added WORDS parameter to $meminit
2015-07-31 10:40:09 +02:00
next_meminit_cursor = cursor;
}
meminit_size++;
next_meminit_cursor++;
meminit_bits.insert(meminit_bits.end(), value->bits.begin(), value->bits.end());
}
else
{
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
block->children.push_back(
std::make_unique<AstNode>(location,
AST_ASSIGN_EQ, std::make_unique<AstNode>(location,
AST_IDENTIFIER, std::make_unique<AstNode>(location,
AST_RANGE, AstNode::mkconst_int(location,
cursor, false))),
std::move(value)));
Added WORDS parameter to $meminit
2015-07-31 10:40:09 +02:00
block->children.back()->children[0]->str = memory->str;
block->children.back()->children[0]->id2ast = memory;
Fixed remaining cases where we check fo wire reg/wire incorrect assignments on Yosys-generated assignments. In this case, offending code was: module top(input in, output out); function func; input arg; func = arg; endfunction assign out = func(in); endmodule
2018-09-18 00:23:40 +02:00
block->children.back()->children[0]->was_checked = true;
Added WORDS parameter to $meminit
2015-07-31 10:40:09 +02:00
}
Added support for $readmemh/$readmemb
2014-10-26 20:33:10 +01:00
cursor += increment;
Fixed finish_addr handling in $readmemh/$readmemb
2016-08-20 13:47:46 +02:00
if ((cursor == finish_addr+increment) || (increment > 0 && cursor > range_max) || (increment < 0 && cursor < range_min))
break;
Added support for $readmemh/$readmemb
2014-10-26 20:33:10 +01:00
}
Fixed finish_addr handling in $readmemh/$readmemb
2016-08-20 13:47:46 +02:00
if ((cursor == finish_addr+increment) || (increment > 0 && cursor > range_max) || (increment < 0 && cursor < range_min))
Added support for $readmemh/$readmemb
2014-10-26 20:33:10 +01:00
break;
}
Added WORDS parameter to $meminit
2015-07-31 10:40:09 +02:00
if (meminit != nullptr) {
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
meminit->children[1] = AstNode::mkconst_bits(location, meminit_bits, false);
meminit->children[3] = AstNode::mkconst_int(location, meminit_size, false);
Added WORDS parameter to $meminit
2015-07-31 10:40:09 +02:00
}
Added support for $readmemh/$readmemb
2014-10-26 20:33:10 +01:00
return block;
}
verilog: significant block scoping improvements This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
2021-01-27 19:30:22 +01:00
// annotate the names of all wires and other named objects in a named generate
// or procedural block; nested blocks are themselves annotated such that the
// prefix is carried forward, but resolution of their children is deferred
void AstNode::expand_genblock(const std::string &prefix)
initial import
2013-01-05 11:13:26 +01:00
{
verilog: fix multiple AST_PREFIX scope resolution issues - Root AST_PREFIX nodes are now subject to genblk expansion to allow them to refer to a locally-visible generate block - Part selects on AST_PREFIX member leafs can now refer to generate block items (previously would not resolve and raise an error) - Add source location information to AST_PREFIX nodes
2021-08-03 02:42:34 +02:00
if (type == AST_IDENTIFIER || type == AST_FCALL || type == AST_TCALL || type == AST_WIRETYPE || type == AST_PREFIX) {
verilog: significant block scoping improvements This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
2021-01-27 19:30:22 +01:00
log_assert(!str.empty());
// search starting in the innermost scope and then stepping outward
for (size_t ppos = prefix.size() - 1; ppos; --ppos) {
if (prefix.at(ppos) != '.') continue;
std::string new_prefix = prefix.substr(0, ppos + 1);
auto attempt_resolve = [&new_prefix](const std::string &ident) -> std::string {
std::string new_name = prefix_id(new_prefix, ident);
if (current_scope.count(new_name))
return new_name;
return {};
};
// attempt to resolve the full identifier
std::string resolved = attempt_resolve(str);
if (!resolved.empty()) {
str = resolved;
break;
Fix generate scoping issues - expand_genblock defers prefixing of items within named sub-blocks - Allow partially-qualified references to local scopes - Handle shadowing within generate blocks - Resolve generate scope references within tasks and functions - Apply generate scoping to genvars - Resolves #2214, resolves #1456
2020-08-01 04:13:05 +02:00
}
initial import
2013-01-05 11:13:26 +01:00
verilog: significant block scoping improvements This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
2021-01-27 19:30:22 +01:00
// attempt to resolve hierarchical prefixes within the identifier,
// as the prefix could refer to a local scope which exists but
// hasn't yet been elaborated
for (size_t spos = str.size() - 1; spos; --spos) {
if (str.at(spos) != '.') continue;
resolved = attempt_resolve(str.substr(0, spos));
if (!resolved.empty()) {
str = resolved + str.substr(spos);
ppos = 1; // break outer loop
break;
}
}
Fix generate scoping issues - expand_genblock defers prefixing of items within named sub-blocks - Allow partially-qualified references to local scopes - Handle shadowing within generate blocks - Resolve generate scope references within tasks and functions - Apply generate scoping to genvars - Resolves #2214, resolves #1456
2020-08-01 04:13:05 +02:00
}
verilog: significant block scoping improvements This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
2021-01-27 19:30:22 +01:00
}
Fix generate scoping issues - expand_genblock defers prefixing of items within named sub-blocks - Allow partially-qualified references to local scopes - Handle shadowing within generate blocks - Resolve generate scope references within tasks and functions - Apply generate scoping to genvars - Resolves #2214, resolves #1456
2020-08-01 04:13:05 +02:00
verilog: significant block scoping improvements This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
2021-01-27 19:30:22 +01:00
auto prefix_node = [&prefix](AstNode* child) {
if (child->str.empty()) return;
std::string new_name = prefix_id(prefix, child->str);
Fix generate scoping issues - expand_genblock defers prefixing of items within named sub-blocks - Allow partially-qualified references to local scopes - Handle shadowing within generate blocks - Resolve generate scope references within tasks and functions - Apply generate scoping to genvars - Resolves #2214, resolves #1456
2020-08-01 04:13:05 +02:00
if (child->type == AST_FUNCTION)
verilog: improved support for recursive functions
2021-01-01 01:23:36 +01:00
child->replace_result_wire_name_in_function(child->str, new_name);
Fix generate scoping issues - expand_genblock defers prefixing of items within named sub-blocks - Allow partially-qualified references to local scopes - Handle shadowing within generate blocks - Resolve generate scope references within tasks and functions - Apply generate scoping to genvars - Resolves #2214, resolves #1456
2020-08-01 04:13:05 +02:00
else
child->str = new_name;
current_scope[new_name] = child;
};
initial import
2013-01-05 11:13:26 +01:00
for (size_t i = 0; i < children.size(); i++) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto* child = children[i].get();
Fix generate scoping issues - expand_genblock defers prefixing of items within named sub-blocks - Allow partially-qualified references to local scopes - Handle shadowing within generate blocks - Resolve generate scope references within tasks and functions - Apply generate scoping to genvars - Resolves #2214, resolves #1456
2020-08-01 04:13:05 +02:00
switch (child->type) {
case AST_WIRE:
case AST_MEMORY:
Correct hierarchical path names for structs and unions
2024-01-04 17:22:07 +01:00
case AST_STRUCT:
case AST_UNION:
Fix generate scoping issues - expand_genblock defers prefixing of items within named sub-blocks - Allow partially-qualified references to local scopes - Handle shadowing within generate blocks - Resolve generate scope references within tasks and functions - Apply generate scoping to genvars - Resolves #2214, resolves #1456
2020-08-01 04:13:05 +02:00
case AST_PARAMETER:
case AST_LOCALPARAM:
case AST_FUNCTION:
case AST_TASK:
case AST_CELL:
case AST_TYPEDEF:
case AST_ENUM_ITEM:
case AST_GENVAR:
prefix_node(child);
break;
case AST_BLOCK:
case AST_GENBLOCK:
if (!child->str.empty())
prefix_node(child);
break;
case AST_ENUM:
add attributes for enumerated values in ilang - information also useful for strongly-typed enums (not implemented) - resolves enum values in ilang part of #1594 - still need to output enums to VCD (or better yet FST) files
2020-02-03 07:12:24 +01:00
current_scope[child->str] = child;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& enode : child->children){
fix enum in generate blocks
2020-01-16 23:05:45 +01:00
log_assert(enode->type == AST_ENUM_ITEM);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
prefix_node(enode.get());
fix enum in generate blocks
2020-01-16 23:05:45 +01:00
}
Fix generate scoping issues - expand_genblock defers prefixing of items within named sub-blocks - Allow partially-qualified references to local scopes - Handle shadowing within generate blocks - Resolve generate scope references within tasks and functions - Apply generate scoping to genvars - Resolves #2214, resolves #1456
2020-08-01 04:13:05 +02:00
break;
default:
break;
fix enum in generate blocks
2020-01-16 23:05:45 +01:00
}
initial import
2013-01-05 11:13:26 +01:00
}
for (size_t i = 0; i < children.size(); i++) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto& child = children[i];
verilog: fix multiple AST_PREFIX scope resolution issues - Root AST_PREFIX nodes are now subject to genblk expansion to allow them to refer to a locally-visible generate block - Part selects on AST_PREFIX member leafs can now refer to generate block items (previously would not resolve and raise an error) - Add source location information to AST_PREFIX nodes
2021-08-03 02:42:34 +02:00
// AST_PREFIX member names should not be prefixed; we recurse into them
// as normal to ensure indices and ranges are properly resolved, and
// then restore the previous string
if (type == AST_PREFIX && i == 1) {
std::string backup_scope_name = child->str;
child->expand_genblock(prefix);
child->str = backup_scope_name;
fix local name resolution in prefix constructs
2019-03-19 01:34:21 +01:00
continue;
verilog: fix multiple AST_PREFIX scope resolution issues - Root AST_PREFIX nodes are now subject to genblk expansion to allow them to refer to a locally-visible generate block - Part selects on AST_PREFIX member leafs can now refer to generate block items (previously would not resolve and raise an error) - Add source location information to AST_PREFIX nodes
2021-08-03 02:42:34 +02:00
}
Fix generate scoping issues - expand_genblock defers prefixing of items within named sub-blocks - Allow partially-qualified references to local scopes - Handle shadowing within generate blocks - Resolve generate scope references within tasks and functions - Apply generate scoping to genvars - Resolves #2214, resolves #1456
2020-08-01 04:13:05 +02:00
// functions/tasks may reference wires, constants, etc. in this scope
if (child->type == AST_FUNCTION || child->type == AST_TASK)
verilog: significant block scoping improvements This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
2021-01-27 19:30:22 +01:00
continue;
// named blocks pick up the current prefix and will expanded later
if ((child->type == AST_GENBLOCK || child->type == AST_BLOCK) && !child->str.empty())
continue;
sv: Switch parser to glr, prep for typedef Signed-off-by: David Shah <dave@ds0.me>
2019-09-19 21:43:13 +02:00
verilog: significant block scoping improvements This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
2021-01-27 19:30:22 +01:00
child->expand_genblock(prefix);
}
initial import
2013-01-05 11:13:26 +01:00
}
verilog: significant block scoping improvements This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
2021-01-27 19:30:22 +01:00
// add implicit AST_GENBLOCK names according to IEEE 1364-2005 Section 12.4.3 or
// IEEE 1800-2017 Section 27.6
void AstNode::label_genblks(std::set<std::string>& existing, int &counter)
initial import
2013-01-05 11:13:26 +01:00
{
verilog: significant block scoping improvements This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
2021-01-27 19:30:22 +01:00
switch (type) {
case AST_GENIF:
case AST_GENFOR:
case AST_GENCASE:
// seeing a proper generate control flow construct increments the
// counter once
++counter;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : children)
verilog: significant block scoping improvements This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
2021-01-27 19:30:22 +01:00
child->label_genblks(existing, counter);
break;
Improved scope resolution of local regs in Verilog+AST frontend
2014-08-05 12:15:53 +02:00
verilog: significant block scoping improvements This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
2021-01-27 19:30:22 +01:00
case AST_GENBLOCK: {
// if this block is unlabeled, generate its corresponding unique name
for (int padding = 0; str.empty(); ++padding) {
std::string candidate = "\\genblk";
for (int i = 0; i < padding; ++i)
candidate += '0';
candidate += std::to_string(counter);
if (!existing.count(candidate))
str = candidate;
}
// within a genblk, the counter starts fresh
std::set<std::string> existing_local = existing;
int counter_local = 0;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : children)
verilog: significant block scoping improvements This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
2021-01-27 19:30:22 +01:00
child->label_genblks(existing_local, counter_local);
break;
Improved scope resolution of local regs in Verilog+AST frontend
2014-08-05 12:15:53 +02:00
}
verilog: significant block scoping improvements This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
2021-01-27 19:30:22 +01:00
default:
// track names which could conflict with implicit genblk names
if (str.rfind("\\genblk", 0) == 0)
existing.insert(str);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : children)
verilog: significant block scoping improvements This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
2021-01-27 19:30:22 +01:00
child->label_genblks(existing, counter);
break;
Improved scope resolution of local regs in Verilog+AST frontend
2014-08-05 12:15:53 +02:00
}
initial import
2013-01-05 11:13:26 +01:00
}
Added AstNode::MEM2REG_FL_CMPLX_LHS
2014-06-17 21:39:25 +02:00
// helper function for mem2reg_as_needed_pass1
dict/pool changes in ast
2014-12-29 03:11:50 +01:00
static void mark_memories_assign_lhs_complex(dict<AstNode*, pool<std::string>> &mem2reg_places,
dict<AstNode*, uint32_t> &mem2reg_candidates, AstNode *that)
Added AstNode::MEM2REG_FL_CMPLX_LHS
2014-06-17 21:39:25 +02:00
{
for (auto &child : that->children)
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
mark_memories_assign_lhs_complex(mem2reg_places, mem2reg_candidates, child.get());
Added AstNode::MEM2REG_FL_CMPLX_LHS
2014-06-17 21:39:25 +02:00
if (that->type == AST_IDENTIFIER && that->id2ast && that->id2ast->type == AST_MEMORY) {
AstNode *mem = that->id2ast;
if (!(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_CMPLX_LHS))
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(*that->location.begin.filename).c_str(), that->location.begin.line));
Added AstNode::MEM2REG_FL_CMPLX_LHS
2014-06-17 21:39:25 +02:00
mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_CMPLX_LHS;
}
}
initial import
2013-01-05 11:13:26 +01:00
// find memories that should be replaced by registers
dict/pool changes in ast
2014-12-29 03:11:50 +01:00
void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg_places,
dict<AstNode*, uint32_t> &mem2reg_candidates, dict<AstNode*, uint32_t> &proc_flags, uint32_t &flags)
initial import
2013-01-05 11:13:26 +01:00
{
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
uint32_t children_flags = 0;
Improve handling of memories used in mem index expressions on LHS of an assignment Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-12 20:12:02 +01:00
int lhs_children_counter = 0;
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
sv: Add support for memory typedefs Signed-off-by: David Shah <dave@ds0.me>
2019-09-20 12:39:15 +02:00
if (type == AST_TYPEDEF)
return; // don't touch content of typedefs
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
if (type == AST_ASSIGN || type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ)
{
Added AstNode::MEM2REG_FL_CMPLX_LHS
2014-06-17 21:39:25 +02:00
// mark all memories that are used in a complex expression on the left side of an assignment
for (auto &lhs_child : children[0]->children)
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
mark_memories_assign_lhs_complex(mem2reg_places, mem2reg_candidates, lhs_child.get());
Added AstNode::MEM2REG_FL_CMPLX_LHS
2014-06-17 21:39:25 +02:00
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
if (children[0]->type == AST_IDENTIFIER && children[0]->id2ast && children[0]->id2ast->type == AST_MEMORY)
{
AstNode *mem = children[0]->id2ast;
// activate mem2reg if this is assigned in an async proc
if (flags & AstNode::MEM2REG_FL_ASYNC) {
if (!(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_SET_ASYNC))
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(*location.begin.filename).c_str(), location.begin.line));
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_SET_ASYNC;
}
// remember if this is assigned blocking (=)
if (type == AST_ASSIGN_EQ) {
if (!(proc_flags[mem] & AstNode::MEM2REG_FL_EQ1))
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(*location.begin.filename).c_str(), location.begin.line));
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
proc_flags[mem] |= AstNode::MEM2REG_FL_EQ1;
}
Only set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for non-init writes, fixes #867 Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-12 20:09:47 +01:00
// for proper (non-init) writes: remember if this is a constant index or not
if ((flags & MEM2REG_FL_INIT) == 0) {
if (children[0]->children.size() && children[0]->children[0]->type == AST_RANGE && children[0]->children[0]->children.size()) {
if (children[0]->children[0]->children[0]->type == AST_CONSTANT)
mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_CONST_LHS;
else
mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_VAR_LHS;
}
Use mem2reg on memories that only have constant-index write ports Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-01 22:35:09 +01:00
}
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
// remember where this is
if (flags & MEM2REG_FL_INIT) {
if (!(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_SET_INIT))
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(*location.begin.filename).c_str(), location.begin.line));
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_SET_INIT;
} else {
if (!(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_SET_ELSE))
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(*location.begin.filename).c_str(), location.begin.line));
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_SET_ELSE;
initial import
2013-01-05 11:13:26 +01:00
}
}
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
Improve handling of memories used in mem index expressions on LHS of an assignment Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-12 20:12:02 +01:00
lhs_children_counter = 1;
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
}
if (type == AST_IDENTIFIER && id2ast && id2ast->type == AST_MEMORY)
{
AstNode *mem = id2ast;
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
if (integer < (unsigned)mem->unpacked_dimensions)
input_error("Insufficient number of array indices for %s.\n", log_id(str));
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
// flag if used after blocking assignment (in same proc)
if ((proc_flags[mem] & AstNode::MEM2REG_FL_EQ1) && !(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_EQ2)) {
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(*location.begin.filename).c_str(), location.begin.line));
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_EQ2;
}
}
ast/simplify: don't bitblast async ROMs declared as `logic`. Fixes #2020.
2020-05-05 06:11:16 +02:00
// also activate if requested, either by using mem2reg attribute or by declaring array as 'wire' instead of 'reg' or 'logic'
if (type == AST_MEMORY && (get_bool_attribute(ID::mem2reg) || (flags & AstNode::MEM2REG_FL_ALL) || !(is_reg || is_logic)))
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
mem2reg_candidates[this] |= AstNode::MEM2REG_FL_FORCED;
initial import
2013-01-05 11:13:26 +01:00
Resolve package types in interfaces (#3658) * Resolve package types in interfaces * Added test for resolving of package types in interfaces
2023-02-13 00:25:39 +01:00
if ((type == AST_MODULE || type == AST_INTERFACE) && get_bool_attribute(ID::mem2reg))
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
children_flags |= AstNode::MEM2REG_FL_ALL;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
dict<AstNode*, uint32_t> *proc_flags_p = nullptr;
Added mem2reg option to verilog frontend
2013-03-24 11:13:32 +01:00
initial import
2013-01-05 11:13:26 +01:00
if (type == AST_ALWAYS) {
Fixed async proc detection in mem2reg
2013-11-21 21:26:56 +01:00
int count_edge_events = 0;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : children)
initial import
2013-01-05 11:13:26 +01:00
if (child->type == AST_POSEDGE || child->type == AST_NEGEDGE)
Fixed async proc detection in mem2reg
2013-11-21 21:26:56 +01:00
count_edge_events++;
if (count_edge_events != 1)
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
children_flags |= AstNode::MEM2REG_FL_ASYNC;
dict/pool changes in ast
2014-12-29 03:11:50 +01:00
proc_flags_p = new dict<AstNode*, uint32_t>;
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
}
Fixes for some of clang scan-build detected issues
2023-01-17 12:58:08 +01:00
else if (type == AST_INITIAL) {
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
children_flags |= AstNode::MEM2REG_FL_INIT;
dict/pool changes in ast
2014-12-29 03:11:50 +01:00
proc_flags_p = new dict<AstNode*, uint32_t>;
initial import
2013-01-05 11:13:26 +01:00
}
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
uint32_t backup_flags = flags;
flags |= children_flags;
Using log_assert() instead of assert()
2014-07-28 11:08:55 +02:00
log_assert((flags & ~0x000000ff) == 0);
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : children)
Improve handling of memories used in mem index expressions on LHS of an assignment Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-12 20:12:02 +01:00
{
if (lhs_children_counter > 0) {
lhs_children_counter--;
if (child->children.size() && child->children[0]->type == AST_RANGE && child->children[0]->children.size()) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& c : child->children[0]->children) {
Improve handling of memories used in mem index expressions on LHS of an assignment Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-12 20:12:02 +01:00
if (proc_flags_p)
c->mem2reg_as_needed_pass1(mem2reg_places, mem2reg_candidates, *proc_flags_p, flags);
else
c->mem2reg_as_needed_pass1(mem2reg_places, mem2reg_candidates, proc_flags, flags);
}
}
} else
if (proc_flags_p)
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
child->mem2reg_as_needed_pass1(mem2reg_places, mem2reg_candidates, *proc_flags_p, flags);
else
child->mem2reg_as_needed_pass1(mem2reg_places, mem2reg_candidates, proc_flags, flags);
Improve handling of memories used in mem index expressions on LHS of an assignment Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-12 20:12:02 +01:00
}
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
flags &= ~children_flags | backup_flags;
if (proc_flags_p) {
Added ENABLE_NDEBUG makefile options
2015-01-24 12:16:46 +01:00
#ifndef NDEBUG
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
for (auto it : *proc_flags_p)
Fixed gcc compiler warnings with release build
2014-02-06 22:49:14 +01:00
log_assert((it.second & ~0xff000000) == 0);
Added ENABLE_NDEBUG makefile options
2015-01-24 12:16:46 +01:00
#endif
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
delete proc_flags_p;
}
initial import
2013-01-05 11:13:26 +01:00
}
dict/pool changes in ast
2014-12-29 03:11:50 +01:00
bool AstNode::mem2reg_check(pool<AstNode*> &mem2reg_set)
Fixed handling of invalid array access in mem2reg code
2014-10-16 00:44:23 +02:00
{
if (type != AST_IDENTIFIER || !id2ast || !mem2reg_set.count(id2ast))
return false;
if (children.empty() || children[0]->type != AST_RANGE || GetSize(children[0]->children) != 1)
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Invalid array access.\n");
Fixed handling of invalid array access in mem2reg code
2014-10-16 00:44:23 +02:00
return true;
}
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
void AstNode::mem2reg_remove(pool<AstNode*> &mem2reg_set)
Fixed access-after-delete bug in mem2reg code
2016-05-27 17:25:33 +02:00
{
log_assert(mem2reg_set.count(this) == 0);
if (mem2reg_set.count(id2ast))
id2ast = nullptr;
for (size_t i = 0; i < children.size(); i++) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
if (mem2reg_set.count(children[i].get()) > 0) {
Fixed access-after-delete bug in mem2reg code
2016-05-27 17:25:33 +02:00
children.erase(children.begin() + (i--));
} else {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
children[i]->mem2reg_remove(mem2reg_set);
Fixed access-after-delete bug in mem2reg code
2016-05-27 17:25:33 +02:00
}
}
}
initial import
2013-01-05 11:13:26 +01:00
// actually replace memories with registers
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod, AstNode *block, AstNode* async_block)
initial import
2013-01-05 11:13:26 +01:00
{
Fixed nested mem2reg
2015-07-29 16:37:08 +02:00
bool did_something = false;
initial import
2013-01-05 11:13:26 +01:00
if (type == AST_BLOCK)
block = this;
Another bugfix in mem2reg code
2016-08-21 13:23:58 +02:00
if (type == AST_FUNCTION || type == AST_TASK)
return false;
sv: Add support for memory typedefs Signed-off-by: David Shah <dave@ds0.me>
2019-09-20 12:39:15 +02:00
if (type == AST_TYPEDEF)
return false;
Fix $readmem[hb] for mem2reg memories, fixes #785 Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-02 18:58:20 +01:00
if (type == AST_MEMINIT && id2ast && mem2reg_set.count(id2ast))
{
log_assert(children[0]->type == AST_CONSTANT);
log_assert(children[1]->type == AST_CONSTANT);
log_assert(children[2]->type == AST_CONSTANT);
verilog: Emit $meminit_v2 cell. Fixes #2447.
2021-05-21 02:27:06 +02:00
log_assert(children[3]->type == AST_CONSTANT);
Fix $readmem[hb] for mem2reg memories, fixes #785 Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-02 18:58:20 +01:00
int cursor = children[0]->asInt(false);
Const data = children[1]->bitsAsConst();
verilog: Emit $meminit_v2 cell. Fixes #2447.
2021-05-21 02:27:06 +02:00
Const en = children[2]->bitsAsConst();
int length = children[3]->asInt(false);
Fix $readmem[hb] for mem2reg memories, fixes #785 Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-02 18:58:20 +01:00
if (length != 0)
{
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto block_owned = std::make_unique<AstNode>(location,
AST_INITIAL, std::make_unique<AstNode>(location,
AST_BLOCK));
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto block = block_owned.get();
mod->children.push_back(std::move(block_owned));
block = block->children[0].get();
Fix $readmem[hb] for mem2reg memories, fixes #785 Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-02 18:58:20 +01:00
int wordsz = GetSize(data) / length;
for (int i = 0; i < length; i++) {
verilog: Emit $meminit_v2 cell. Fixes #2447.
2021-05-21 02:27:06 +02:00
int pos = 0;
while (pos < wordsz) {
if (en[pos] != State::S1) {
pos++;
} else {
int epos = pos + 1;
while (epos < wordsz && en[epos] == State::S1)
epos++;
int clen = epos - pos;
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto range = std::make_unique<AstNode>(location,
AST_RANGE, AstNode::mkconst_int(location,
cursor+i, false));
verilog: Emit $meminit_v2 cell. Fixes #2447.
2021-05-21 02:27:06 +02:00
if (pos != 0 || epos != wordsz) {
int left;
int right;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto& mrange = id2ast->children[0];
verilog: Emit $meminit_v2 cell. Fixes #2447.
2021-05-21 02:27:06 +02:00
if (mrange->range_left < mrange->range_right) {
right = mrange->range_right - pos;
left = mrange->range_right - epos + 1;
} else {
right = mrange->range_right + pos;
left = mrange->range_right + epos - 1;
}
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
range = std::make_unique<AstNode>(location,
AST_MULTIRANGE, std::move(range), std::make_unique<AstNode>(location,
AST_RANGE,
AstNode::mkconst_int(location, left, true),
AstNode::mkconst_int(location, right, true)));
verilog: Emit $meminit_v2 cell. Fixes #2447.
2021-05-21 02:27:06 +02:00
}
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto target = std::make_unique<AstNode>(location, AST_IDENTIFIER, std::move(range));
verilog: Emit $meminit_v2 cell. Fixes #2447.
2021-05-21 02:27:06 +02:00
target->str = str;
target->id2ast = id2ast;
target->was_checked = true;
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
block->children.push_back(std::make_unique<AstNode>(location,
AST_ASSIGN_EQ,
std::move(target),
mkconst_bits(location,
data.extract(i*wordsz + pos, clen).to_bits(),
false)));
verilog: Emit $meminit_v2 cell. Fixes #2447.
2021-05-21 02:27:06 +02:00
pos = epos;
}
}
Fix $readmem[hb] for mem2reg memories, fixes #785 Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-02 18:58:20 +01:00
}
}
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto newNode = std::make_unique<AstNode>(location, AST_NONE);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
newNode->cloneInto(*this);
Fix $readmem[hb] for mem2reg memories, fixes #785 Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-02 18:58:20 +01:00
did_something = true;
}
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
if (type == AST_ASSIGN && block == nullptr && children[0]->mem2reg_check(mem2reg_set))
Another bugfix in mem2reg code
2016-08-21 13:23:58 +02:00
{
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
if (async_block == nullptr) {
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto async_block_owned = std::make_unique<AstNode>(location, AST_ALWAYS, std::make_unique<AstNode>(location, AST_BLOCK));
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
async_block = async_block_owned.get();
mod->children.push_back(std::move(async_block_owned));
Another bugfix in mem2reg code
2016-08-21 13:23:58 +02:00
}
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto newNode = clone();
Another bugfix in mem2reg code
2016-08-21 13:23:58 +02:00
newNode->type = AST_ASSIGN_EQ;
Fixed issue #630 by fixing a minor typo in the previous commit (as well as a non critical minor code optimization)
2018-09-24 23:32:57 +02:00
newNode->children[0]->was_checked = true;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
async_block->children[0]->children.push_back(std::move(newNode));
Another bugfix in mem2reg code
2016-08-21 13:23:58 +02:00
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
newNode = std::make_unique<AstNode>(location, AST_NONE);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
newNode->cloneInto(*this);
Another bugfix in mem2reg code
2016-08-21 13:23:58 +02:00
did_something = true;
}
if ((type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ) && children[0]->mem2reg_check(mem2reg_set) &&
children[0]->children[0]->children[0]->type != AST_CONSTANT)
initial import
2013-01-05 11:13:26 +01:00
{
std::stringstream sstr;
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
sstr << "$mem2reg_wr$" << children[0]->str << "$" << RTLIL::encode_filename(*location.begin.filename) << ":" << location.begin.line << "$" << (autoidx++);
initial import
2013-01-05 11:13:26 +01:00
std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA";
int mem_width, mem_size, addr_bits;
Some fixes in handling of signed arrays
2016-11-01 23:17:43 +01:00
bool mem_signed = children[0]->id2ast->is_signed;
initial import
2013-01-05 11:13:26 +01:00
children[0]->id2ast->meminfo(mem_width, mem_size, addr_bits);
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto wire_addr = std::make_unique<AstNode>(location, AST_WIRE, std::make_unique<AstNode>(location, AST_RANGE, mkconst_int(location, addr_bits-1, true), mkconst_int(location, 0, true)));
initial import
2013-01-05 11:13:26 +01:00
wire_addr->str = id_addr;
wire_addr->is_reg = true;
Modified errors into warnings No longer false warnings for memories and assertions
2018-06-05 16:44:24 +02:00
wire_addr->was_checked = true;
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
wire_addr->set_attribute(ID::nosync, AstNode::mkconst_int(location, 1, false));
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (wire_addr->simplify(true, 1, -1, false)) { }
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
mod->children.push_back(std::move(wire_addr));
initial import
2013-01-05 11:13:26 +01:00
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto wire_data = std::make_unique<AstNode>(location, AST_WIRE, std::make_unique<AstNode>(location, AST_RANGE, mkconst_int(location, mem_width-1, true), mkconst_int(location, 0, true)));
initial import
2013-01-05 11:13:26 +01:00
wire_data->str = id_data;
wire_data->is_reg = true;
Modified errors into warnings No longer false warnings for memories and assertions
2018-06-05 16:44:24 +02:00
wire_data->was_checked = true;
Some fixes in handling of signed arrays
2016-11-01 23:17:43 +01:00
wire_data->is_signed = mem_signed;
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
wire_data->set_attribute(ID::nosync, AstNode::mkconst_int(location, 1, false));
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (wire_data->simplify(true, 1, -1, false)) { }
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
mod->children.push_back(std::move(wire_data));
initial import
2013-01-05 11:13:26 +01:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
log_assert(block != nullptr);
initial import
2013-01-05 11:13:26 +01:00
size_t assign_idx = 0;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
while (assign_idx < block->children.size() && block->children[assign_idx].get() != this)
initial import
2013-01-05 11:13:26 +01:00
assign_idx++;
Using log_assert() instead of assert()
2014-07-28 11:08:55 +02:00
log_assert(assign_idx < block->children.size());
initial import
2013-01-05 11:13:26 +01:00
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto assign_addr = std::make_unique<AstNode>(location, AST_ASSIGN_EQ, std::make_unique<AstNode>(location, AST_IDENTIFIER), children[0]->children[0]->children[0]->clone());
initial import
2013-01-05 11:13:26 +01:00
assign_addr->children[0]->str = id_addr;
Fixed issue #630 by fixing a minor typo in the previous commit (as well as a non critical minor code optimization)
2018-09-24 23:32:57 +02:00
assign_addr->children[0]->was_checked = true;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
block->children.insert(block->children.begin()+assign_idx+1, std::move(assign_addr));
initial import
2013-01-05 11:13:26 +01:00
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto case_node = std::make_unique<AstNode>(location, AST_CASE, std::make_unique<AstNode>(location, AST_IDENTIFIER));
initial import
2013-01-05 11:13:26 +01:00
case_node->children[0]->str = id_addr;
for (int i = 0; i < mem_size; i++) {
if (children[0]->children[0]->children[0]->type == AST_CONSTANT && int(children[0]->children[0]->children[0]->integer) != i)
continue;
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto cond_node = std::make_unique<AstNode>(location, AST_COND, AstNode::mkconst_int(location, i, false, addr_bits), std::make_unique<AstNode>(location, AST_BLOCK));
auto assign_reg = std::make_unique<AstNode>(location, type, std::make_unique<AstNode>(location, AST_IDENTIFIER), std::make_unique<AstNode>(location, AST_IDENTIFIER));
Added support for bit/part select to mem2reg rewriter
2014-07-17 13:49:32 +02:00
if (children[0]->children.size() == 2)
assign_reg->children[0]->children.push_back(children[0]->children[1]->clone());
initial import
2013-01-05 11:13:26 +01:00
assign_reg->children[0]->str = stringf("%s[%d]", children[0]->str.c_str(), i);
assign_reg->children[1]->str = id_data;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
cond_node->children[1]->children.push_back(std::move(assign_reg));
case_node->children.push_back(std::move(cond_node));
initial import
2013-01-05 11:13:26 +01:00
}
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
// fixup on the full hierarchy below case_node
case_node->fixup_hierarchy_flags(true);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
block->children.insert(block->children.begin()+assign_idx+2, std::move(case_node));
initial import
2013-01-05 11:13:26 +01:00
children[0]->delete_children();
children[0]->range_valid = false;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
children[0]->id2ast = nullptr;
initial import
2013-01-05 11:13:26 +01:00
children[0]->str = id_data;
Another fix in mem2reg ast simplify logic
2013-03-24 10:42:08 +01:00
type = AST_ASSIGN_EQ;
Fixed remaining cases where we check fo wire reg/wire incorrect assignments on Yosys-generated assignments. In this case, offending code was: module top(input in, output out); function func; input arg; func = arg; endfunction assign out = func(in); endmodule
2018-09-18 00:23:40 +02:00
children[0]->was_checked = true;
Fixed nested mem2reg
2015-07-29 16:37:08 +02:00
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
fixup_hierarchy_flags();
Fixed nested mem2reg
2015-07-29 16:37:08 +02:00
did_something = true;
initial import
2013-01-05 11:13:26 +01:00
}
Fixed handling of invalid array access in mem2reg code
2014-10-16 00:44:23 +02:00
if (mem2reg_check(mem2reg_set))
initial import
2013-01-05 11:13:26 +01:00
{
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
std::unique_ptr<AstNode> bit_part_sel = nullptr;
Added support for bit/part select to mem2reg rewriter
2014-07-17 13:49:32 +02:00
if (children.size() == 2)
bit_part_sel = children[1]->clone();
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
if (children[0]->children[0]->type == AST_CONSTANT)
{
int id = children[0]->children[0]->integer;
mem2reg: tolerate out of bounds constant accesses This brings the mem2reg behavior in line with the nomem2reg behavior.
2021-05-27 00:22:31 +02:00
int left = id2ast->children[1]->children[0]->integer;
int right = id2ast->children[1]->children[1]->integer;
bool valid_const_access =
(left <= id && id <= right) ||
(right <= id && id <= left);
if (valid_const_access)
{
str = stringf("%s[%d]", str.c_str(), id);
delete_children();
range_valid = false;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
id2ast = nullptr;
mem2reg: tolerate out of bounds constant accesses This brings the mem2reg behavior in line with the nomem2reg behavior.
2021-05-27 00:22:31 +02:00
}
else
{
int width;
if (bit_part_sel)
{
Add support for packed multidimensional arrays * Generalization of dimensions metadata (also simplifies $size et al.) * Parsing and elaboration of multidimensional packed ranges
2024-01-25 07:28:15 +01:00
// bit_part_sel->dumpAst(nullptr, "? ");
mem2reg: tolerate out of bounds constant accesses This brings the mem2reg behavior in line with the nomem2reg behavior.
2021-05-27 00:22:31 +02:00
if (bit_part_sel->children.size() == 1)
width = 0;
else
width = bit_part_sel->children[0]->integer -
bit_part_sel->children[1]->integer;
bit_part_sel = nullptr;
}
else
{
width = id2ast->children[0]->children[0]->integer -
id2ast->children[0]->children[1]->integer;
}
width = abs(width) + 1;
initial import
2013-01-05 11:13:26 +01:00
mem2reg: tolerate out of bounds constant accesses This brings the mem2reg behavior in line with the nomem2reg behavior.
2021-05-27 00:22:31 +02:00
delete_children();
std::vector<RTLIL::State> x_bits;
for (int i = 0; i < width; i++)
x_bits.push_back(RTLIL::State::Sx);
frontends/ast: More usage of auto For consistency.
2025-08-08 07:10:16 +02:00
auto constant = AstNode::mkconst_bits(location, x_bits, false);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
constant->cloneInto(*this);
mem2reg: tolerate out of bounds constant accesses This brings the mem2reg behavior in line with the nomem2reg behavior.
2021-05-27 00:22:31 +02:00
}
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
}
else
{
std::stringstream sstr;
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
sstr << "$mem2reg_rd$" << str << "$" << RTLIL::encode_filename(*location.begin.filename) << ":" << location.begin.line << "$" << (autoidx++);
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA";
int mem_width, mem_size, addr_bits;
Some fixes in handling of signed arrays
2016-11-01 23:17:43 +01:00
bool mem_signed = id2ast->is_signed;
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
id2ast->meminfo(mem_width, mem_size, addr_bits);
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto wire_addr = std::make_unique<AstNode>(location, AST_WIRE, std::make_unique<AstNode>(location, AST_RANGE, mkconst_int(location, addr_bits-1, true), mkconst_int(location, 0, true)));
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
wire_addr->str = id_addr;
wire_addr->is_reg = true;
Modified errors into warnings No longer false warnings for memories and assertions
2018-06-05 16:44:24 +02:00
wire_addr->was_checked = true;
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
if (block)
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
wire_addr->set_attribute(ID::nosync, AstNode::mkconst_int(location, 1, false));
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (wire_addr->simplify(true, 1, -1, false)) { }
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
mod->children.push_back(std::move(wire_addr));
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto wire_data = std::make_unique<AstNode>(location, AST_WIRE, std::make_unique<AstNode>(location, AST_RANGE, mkconst_int(location, mem_width-1, true), mkconst_int(location, 0, true)));
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
wire_data->str = id_data;
wire_data->is_reg = true;
Modified errors into warnings No longer false warnings for memories and assertions
2018-06-05 16:44:24 +02:00
wire_data->was_checked = true;
Some fixes in handling of signed arrays
2016-11-01 23:17:43 +01:00
wire_data->is_signed = mem_signed;
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
if (block)
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
wire_data->set_attribute(ID::nosync, AstNode::mkconst_int(location, 1, false));
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (wire_data->simplify(true, 1, -1, false)) { }
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
mod->children.push_back(std::move(wire_data));
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto assign_addr = std::make_unique<AstNode>(location, block ? AST_ASSIGN_EQ : AST_ASSIGN, std::make_unique<AstNode>(location, AST_IDENTIFIER), children[0]->children[0]->clone());
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
assign_addr->children[0]->str = id_addr;
Modified errors into warnings No longer false warnings for memories and assertions
2018-06-05 16:44:24 +02:00
assign_addr->children[0]->was_checked = true;
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto case_node = std::make_unique<AstNode>(location, AST_CASE, std::make_unique<AstNode>(location, AST_IDENTIFIER));
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
case_node->children[0]->str = id_addr;
for (int i = 0; i < mem_size; i++) {
if (children[0]->children[0]->type == AST_CONSTANT && int(children[0]->children[0]->integer) != i)
continue;
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto cond_node = std::make_unique<AstNode>(location, AST_COND, AstNode::mkconst_int(location, i, false, addr_bits), std::make_unique<AstNode>(location, AST_BLOCK));
auto assign_reg = std::make_unique<AstNode>(location, AST_ASSIGN_EQ, std::make_unique<AstNode>(location, AST_IDENTIFIER), std::make_unique<AstNode>(location, AST_IDENTIFIER));
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
assign_reg->children[0]->str = id_data;
Modified errors into warnings No longer false warnings for memories and assertions
2018-06-05 16:44:24 +02:00
assign_reg->children[0]->was_checked = true;
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
assign_reg->children[1]->str = stringf("%s[%d]", str.c_str(), i);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
cond_node->children[1]->children.push_back(std::move(assign_reg));
case_node->children.push_back(std::move(cond_node));
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
}
initial import
2013-01-05 11:13:26 +01:00
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
std::vector<RTLIL::State> x_bits;
for (int i = 0; i < mem_width; i++)
x_bits.push_back(RTLIL::State::Sx);
initial import
2013-01-05 11:13:26 +01:00
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto cond_node = std::make_unique<AstNode>(location, AST_COND, std::make_unique<AstNode>(location, AST_DEFAULT), std::make_unique<AstNode>(location, AST_BLOCK));
auto assign_reg = std::make_unique<AstNode>(location, AST_ASSIGN_EQ, std::make_unique<AstNode>(location, AST_IDENTIFIER), AstNode::mkconst_bits(location, x_bits, false));
initial import
2013-01-05 11:13:26 +01:00
assign_reg->children[0]->str = id_data;
Modified errors into warnings No longer false warnings for memories and assertions
2018-06-05 16:44:24 +02:00
assign_reg->children[0]->was_checked = true;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
cond_node->children[1]->children.push_back(std::move(assign_reg));
case_node->children.push_back(std::move(cond_node));
Another fix in mem2reg ast simplify logic
2013-03-24 10:42:08 +01:00
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
// fixup on the full hierarchy below case_node
case_node->fixup_hierarchy_flags(true);
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
if (block)
{
size_t assign_idx = 0;
while (assign_idx < block->children.size() && !block->children[assign_idx]->contains(this))
assign_idx++;
Using log_assert() instead of assert()
2014-07-28 11:08:55 +02:00
log_assert(assign_idx < block->children.size());
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
block->children.insert(block->children.begin()+assign_idx, std::move(case_node));
block->children.insert(block->children.begin()+assign_idx, std::move(assign_addr));
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
}
else
{
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto proc = std::make_unique<AstNode>(location, AST_ALWAYS, std::make_unique<AstNode>(location, AST_BLOCK, std::move(case_node)));
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
mod->children.push_back(std::move(proc));
mod->children.push_back(std::move(assign_addr));
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
mod->fixup_hierarchy_flags();
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
}
initial import
2013-01-05 11:13:26 +01:00
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
delete_children();
range_valid = false;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
id2ast = nullptr;
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
str = id_data;
initial import
2013-01-05 11:13:26 +01:00
}
Added support for bit/part select to mem2reg rewriter
2014-07-17 13:49:32 +02:00
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
if (bit_part_sel) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
children.push_back(std::move(bit_part_sel));
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
fixup_hierarchy_flags();
}
Fix bug in AstNode::mem2reg_as_needed_pass2()
2017-01-15 13:52:50 +01:00
did_something = true;
initial import
2013-01-05 11:13:26 +01:00
}
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
log_assert(id2ast == nullptr || mem2reg_set.count(id2ast) == 0);
std::vector<AstNode*> children_list;
for (auto& child : children)
children_list.push_back(child.get());
initial import
2013-01-05 11:13:26 +01:00
Added nosync attribute and some async reset related fixes
2013-03-25 17:13:14 +01:00
for (size_t i = 0; i < children_list.size(); i++)
Another bugfix in mem2reg code
2016-08-21 13:23:58 +02:00
if (children_list[i]->mem2reg_as_needed_pass2(mem2reg_set, mod, block, async_block))
Fixed nested mem2reg
2015-07-29 16:37:08 +02:00
did_something = true;
return did_something;
initial import
2013-01-05 11:13:26 +01:00
}
Spell check (by Larry Doolittle)
2015-08-14 10:56:05 +02:00
// calculate memory dimensions
initial import
2013-01-05 11:13:26 +01:00
void AstNode::meminfo(int &mem_width, int &mem_size, int &addr_bits)
{
Using log_assert() instead of assert()
2014-07-28 11:08:55 +02:00
log_assert(type == AST_MEMORY);
initial import
2013-01-05 11:13:26 +01:00
mem_width = children[0]->range_left - children[0]->range_right + 1;
mem_size = children[1]->range_left - children[1]->range_right;
if (mem_size < 0)
mem_size *= -1;
Import more std:: stuff into Yosys namespace
2015-10-25 19:30:49 +01:00
mem_size += min(children[1]->range_left, children[1]->range_right) + 1;
initial import
2013-01-05 11:13:26 +01:00
addr_bits = 1;
while ((1 << addr_bits) < mem_size)
addr_bits++;
}
Add latch detection for use_case_method in part-select write, fixes #2040 Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-06-04 23:10:03 +02:00
bool AstNode::detect_latch(const std::string &var)
{
switch (type)
{
case AST_ALWAYS:
for (auto &c : children)
{
switch (c->type)
{
case AST_POSEDGE:
case AST_NEGEDGE:
return false;
Add AST_EDGE support to AstNode::detect_latch(), fixes #2241 Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-07-10 18:41:13 +02:00
case AST_EDGE:
break;
Add latch detection for use_case_method in part-select write, fixes #2040 Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-06-04 23:10:03 +02:00
case AST_BLOCK:
if (!c->detect_latch(var))
return false;
break;
default:
log_abort();
}
}
return true;
case AST_BLOCK:
for (auto &c : children)
if (!c->detect_latch(var))
return false;
return true;
case AST_CASE:
{
bool r = true;
for (auto &c : children) {
if (c->type == AST_COND) {
if (c->children.at(1)->detect_latch(var))
return true;
r = false;
}
if (c->type == AST_DEFAULT) {
if (c->children.at(0)->detect_latch(var))
return true;
r = false;
}
}
return r;
}
case AST_ASSIGN_EQ:
case AST_ASSIGN_LE:
if (children.at(0)->type == AST_IDENTIFIER &&
children.at(0)->children.empty() && children.at(0)->str == var)
return false;
return true;
default:
return true;
}
}
verilog: refactored constant function evaluation Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
2021-01-27 19:21:13 +01:00
bool AstNode::has_const_only_constructs()
improved const function support
2014-06-06 22:55:02 +02:00
{
if (type == AST_WHILE || type == AST_REPEAT)
return true;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : children)
verilog: refactored constant function evaluation Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
2021-01-27 19:21:13 +01:00
if (child->has_const_only_constructs())
improved const function support
2014-06-06 22:55:02 +02:00
return true;
return false;
}
Only run derive on blackbox modules when ports have dynamic size Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-02 21:36:46 +01:00
bool AstNode::is_simple_const_expr()
{
if (type == AST_IDENTIFIER)
return false;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : children)
Only run derive on blackbox modules when ports have dynamic size Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-02 21:36:46 +01:00
if (!child->is_simple_const_expr())
return false;
return true;
}
Created basic support for function calls in parameter values
2014-02-14 19:56:44 +01:00
// helper function for AstNode::eval_const_function()
verilog: refactored constant function evaluation Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
2021-01-27 19:21:13 +01:00
bool AstNode::replace_variables(std::map<std::string, AstNode::varinfo_t> &variables, AstNode *fcall, bool must_succeed)
Created basic support for function calls in parameter values
2014-02-14 19:56:44 +01:00
{
if (type == AST_IDENTIFIER && variables.count(str)) {
rtlil: represent Const strings as std::string
2024-10-09 19:39:45 +02:00
int offset = variables.at(str).offset, width = variables.at(str).val.size();
Created basic support for function calls in parameter values
2014-02-14 19:56:44 +01:00
if (!children.empty()) {
verilog: refactored constant function evaluation Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
2021-01-27 19:21:13 +01:00
if (children.size() != 1 || children.at(0)->type != AST_RANGE) {
if (!must_succeed)
return false;
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Memory access in constant function is not supported\n%s: ...called from here.\n",
frontend: Make helper functions for printing locations.
2021-02-23 19:22:53 +01:00
fcall->loc_string().c_str());
verilog: refactored constant function evaluation Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
2021-01-27 19:21:13 +01:00
}
if (!children.at(0)->replace_variables(variables, fcall, must_succeed))
return false;
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (simplify(true, 1, -1, false)) { }
verilog: refactored constant function evaluation Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
2021-01-27 19:21:13 +01:00
if (!children.at(0)->range_valid) {
if (!must_succeed)
return false;
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Non-constant range\n%s: ... called from here.\n",
frontend: Make helper functions for printing locations.
2021-02-23 19:22:53 +01:00
fcall->loc_string().c_str());
verilog: refactored constant function evaluation Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
2021-01-27 19:21:13 +01:00
}
Import more std:: stuff into Yosys namespace
2015-10-25 19:30:49 +01:00
offset = min(children.at(0)->range_left, children.at(0)->range_right);
width = min(std::abs(children.at(0)->range_left - children.at(0)->range_right) + 1, width);
Created basic support for function calls in parameter values
2014-02-14 19:56:44 +01:00
}
offset -= variables.at(str).offset;
verilog: fix const func eval with upto variables
2022-01-12 07:51:08 +01:00
if (variables.at(str).range_swapped)
offset = -offset;
rtlil: represent Const strings as std::string
2024-10-09 19:39:45 +02:00
std::vector<RTLIL::State> &var_bits = variables.at(str).val.bits();
Created basic support for function calls in parameter values
2014-02-14 19:56:44 +01:00
std::vector<RTLIL::State> new_bits(var_bits.begin() + offset, var_bits.begin() + offset + width);
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto newNode = mkconst_bits(location, new_bits, variables.at(str).is_signed);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
newNode->cloneInto(*this);
verilog: refactored constant function evaluation Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
2021-01-27 19:21:13 +01:00
return true;
Created basic support for function calls in parameter values
2014-02-14 19:56:44 +01:00
}
for (auto &child : children)
verilog: refactored constant function evaluation Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
2021-01-27 19:21:13 +01:00
if (!child->replace_variables(variables, fcall, must_succeed))
return false;
return true;
Created basic support for function calls in parameter values
2014-02-14 19:56:44 +01:00
}
verilog: refactored constant function evaluation Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
2021-01-27 19:21:13 +01:00
// attempt to statically evaluate a functions with all-const arguments
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
std::unique_ptr<AstNode> AstNode::eval_const_function(AstNode *fcall, bool must_succeed)
Created basic support for function calls in parameter values
2014-02-14 19:56:44 +01:00
{
verilog: refactored constant function evaluation Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
2021-01-27 19:21:13 +01:00
std::map<std::string, AstNode*> backup_scope = current_scope;
Created basic support for function calls in parameter values
2014-02-14 19:56:44 +01:00
std::map<std::string, AstNode::varinfo_t> variables;
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
auto block = std::make_unique<AstNode>(location, AST_BLOCK);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
std::unique_ptr<AstNode> result = nullptr;
Created basic support for function calls in parameter values
2014-02-14 19:56:44 +01:00
size_t argidx = 0;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : children)
Created basic support for function calls in parameter values
2014-02-14 19:56:44 +01:00
{
fix functions with no block (but single statement, loop, etc.)
2014-06-06 21:29:23 +02:00
block->children.push_back(child->clone());
Created basic support for function calls in parameter values
2014-02-14 19:56:44 +01:00
}
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
block->set_in_param_flag(true);
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
std::vector<std::unique_ptr<AstNode>> temporary_nodes;
Created basic support for function calls in parameter values
2014-02-14 19:56:44 +01:00
while (!block->children.empty())
{
frontends/ast: More usage of auto For consistency.
2025-08-08 07:10:16 +02:00
auto& stmt = block->children.front();
Created basic support for function calls in parameter values
2014-02-14 19:56:44 +01:00
#if 0
log("-----------------------------------\n");
for (auto &it : variables)
log("%20s %40s\n", it.first.c_str(), log_signal(it.second.val));
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
stmt->dumpAst(nullptr, "stmt> ");
Created basic support for function calls in parameter values
2014-02-14 19:56:44 +01:00
#endif
Allow blocks with declarations within constant functions
2020-07-25 18:16:12 +02:00
if (stmt->type == AST_WIRE)
{
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (stmt->simplify(true, 1, -1, false)) { }
verilog: refactored constant function evaluation Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
2021-01-27 19:21:13 +01:00
if (!stmt->range_valid) {
if (!must_succeed)
goto finished;
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
stmt->input_error("Can't determine size of variable %s\n%s: ... called from here.\n",
frontend: Make helper functions for printing locations.
2021-02-23 19:22:53 +01:00
stmt->str.c_str(), fcall->loc_string().c_str());
verilog: refactored constant function evaluation Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
2021-01-27 19:21:13 +01:00
}
verilog: fix sizing of constant args for tasks/functions - Simplify synthetic localparams for normal calls to update their width - This step was inadvertently removed alongside `added_mod_children` - Support redeclaration of constant function arguments - `eval_const_function` never correctly handled this, but the issue was not exposed in the existing tests until the recent change to always attempt constant function evaluation when all-const args are used - Check asserts in const_arg_loop and const_func tests - Add coverage for width mismatch error cases
2021-02-21 20:45:21 +01:00
AstNode::varinfo_t &variable = variables[stmt->str];
int width = abs(stmt->range_left - stmt->range_right) + 1;
// if this variable has already been declared as an input, check the
// sizes match if it already had an explicit size
if (variable.arg && variable.explicitly_sized && variable.val.size() != width) {
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
input_error("Incompatible re-declaration of constant function wire %s.\n", stmt->str.c_str());
verilog: fix sizing of constant args for tasks/functions - Simplify synthetic localparams for normal calls to update their width - This step was inadvertently removed alongside `added_mod_children` - Support redeclaration of constant function arguments - `eval_const_function` never correctly handled this, but the issue was not exposed in the existing tests until the recent change to always attempt constant function evaluation when all-const args are used - Check asserts in const_arg_loop and const_func tests - Add coverage for width mismatch error cases
2021-02-21 20:45:21 +01:00
}
variable.val = RTLIL::Const(RTLIL::State::Sx, width);
verilog: fix const func eval with upto variables
2022-01-12 07:51:08 +01:00
variable.offset = stmt->range_swapped ? stmt->range_left : stmt->range_right;
variable.range_swapped = stmt->range_swapped;
verilog: fix sizing of constant args for tasks/functions - Simplify synthetic localparams for normal calls to update their width - This step was inadvertently removed alongside `added_mod_children` - Support redeclaration of constant function arguments - `eval_const_function` never correctly handled this, but the issue was not exposed in the existing tests until the recent change to always attempt constant function evaluation when all-const args are used - Check asserts in const_arg_loop and const_func tests - Add coverage for width mismatch error cases
2021-02-21 20:45:21 +01:00
variable.is_signed = stmt->is_signed;
variable.explicitly_sized = stmt->children.size() &&
stmt->children.back()->type == AST_RANGE;
// identify the argument corresponding to this wire, if applicable
Merge branch 'const-func-block-var' of https://github.com/zachjs/yosys into zachjs-const-func-block-var Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-08-18 17:27:51 +02:00
if (stmt->is_input && argidx < fcall->children.size()) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
variable.arg = fcall->children.at(argidx++).get();
verilog: fix sizing of constant args for tasks/functions - Simplify synthetic localparams for normal calls to update their width - This step was inadvertently removed alongside `added_mod_children` - Support redeclaration of constant function arguments - `eval_const_function` never correctly handled this, but the issue was not exposed in the existing tests until the recent change to always attempt constant function evaluation when all-const args are used - Check asserts in const_arg_loop and const_func tests - Add coverage for width mismatch error cases
2021-02-21 20:45:21 +01:00
}
// load the constant arg's value into this variable
if (variable.arg) {
if (variable.arg->type == AST_CONSTANT) {
variable.val = variable.arg->bitsAsConst(width);
Merge branch 'const-func-block-var' of https://github.com/zachjs/yosys into zachjs-const-func-block-var Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-08-18 17:27:51 +02:00
} else {
verilog: fix sizing of constant args for tasks/functions - Simplify synthetic localparams for normal calls to update their width - This step was inadvertently removed alongside `added_mod_children` - Support redeclaration of constant function arguments - `eval_const_function` never correctly handled this, but the issue was not exposed in the existing tests until the recent change to always attempt constant function evaluation when all-const args are used - Check asserts in const_arg_loop and const_func tests - Add coverage for width mismatch error cases
2021-02-21 20:45:21 +01:00
log_assert(variable.arg->type == AST_REALVALUE);
variable.val = variable.arg->realAsConst(width);
Merge branch 'const-func-block-var' of https://github.com/zachjs/yosys into zachjs-const-func-block-var Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-08-18 17:27:51 +02:00
}
}
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_scope[stmt->str] = stmt.get();
temporary_nodes.push_back(std::move(stmt));
Allow blocks with declarations within constant functions
2020-07-25 18:16:12 +02:00
block->children.erase(block->children.begin());
continue;
}
log_assert(variables.count(str) != 0);
Allow localparams in constant functions
2020-08-21 02:09:54 +02:00
if (stmt->type == AST_LOCALPARAM)
{
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (stmt->simplify(true, 1, -1, false)) { }
Allow localparams in constant functions
2020-08-21 02:09:54 +02:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
current_scope[stmt->str] = stmt.get();
temporary_nodes.push_back(std::move(stmt));
Allow localparams in constant functions
2020-08-21 02:09:54 +02:00
block->children.erase(block->children.begin());
continue;
}
Created basic support for function calls in parameter values
2014-02-14 19:56:44 +01:00
if (stmt->type == AST_ASSIGN_EQ)
{
Fixed complexity of assigning to vectors in constant functions
2015-10-01 12:15:35 +02:00
if (stmt->children.at(0)->type == AST_IDENTIFIER && stmt->children.at(0)->children.size() != 0 &&
stmt->children.at(0)->children.at(0)->type == AST_RANGE)
verilog: refactored constant function evaluation Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
2021-01-27 19:21:13 +01:00
if (!stmt->children.at(0)->children.at(0)->replace_variables(variables, fcall, must_succeed))
goto finished;
if (!stmt->children.at(1)->replace_variables(variables, fcall, must_succeed))
goto finished;
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (stmt->simplify(true, 1, -1, false)) { }
Created basic support for function calls in parameter values
2014-02-14 19:56:44 +01:00
improved ast simplify of const functions
2014-06-06 17:40:45 +02:00
if (stmt->type != AST_ASSIGN_EQ)
continue;
verilog: refactored constant function evaluation Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
2021-01-27 19:21:13 +01:00
if (stmt->children.at(1)->type != AST_CONSTANT) {
if (!must_succeed)
goto finished;
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
stmt->input_error("Non-constant expression in constant function\n%s: ... called from here. X\n",
frontend: Make helper functions for printing locations.
2021-02-23 19:22:53 +01:00
fcall->loc_string().c_str());
verilog: refactored constant function evaluation Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
2021-01-27 19:21:13 +01:00
}
Created basic support for function calls in parameter values
2014-02-14 19:56:44 +01:00
verilog: refactored constant function evaluation Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
2021-01-27 19:21:13 +01:00
if (stmt->children.at(0)->type != AST_IDENTIFIER) {
if (!must_succeed)
goto finished;
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
stmt->input_error("Unsupported composite left hand side in constant function\n%s: ... called from here.\n",
frontend: Make helper functions for printing locations.
2021-02-23 19:22:53 +01:00
fcall->loc_string().c_str());
verilog: refactored constant function evaluation Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
2021-01-27 19:21:13 +01:00
}
Created basic support for function calls in parameter values
2014-02-14 19:56:44 +01:00
verilog: refactored constant function evaluation Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
2021-01-27 19:21:13 +01:00
if (!variables.count(stmt->children.at(0)->str)) {
if (!must_succeed)
goto finished;
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
stmt->input_error("Assignment to non-local variable in constant function\n%s: ... called from here.\n",
frontend: Make helper functions for printing locations.
2021-02-23 19:22:53 +01:00
fcall->loc_string().c_str());
verilog: refactored constant function evaluation Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
2021-01-27 19:21:13 +01:00
}
Created basic support for function calls in parameter values
2014-02-14 19:56:44 +01:00
improved const function support
2014-06-06 22:55:02 +02:00
if (stmt->children.at(0)->children.empty()) {
rtlil: represent Const strings as std::string
2024-10-09 19:39:45 +02:00
variables[stmt->children.at(0)->str].val = stmt->children.at(1)->bitsAsConst(variables[stmt->children.at(0)->str].val.size());
improved const function support
2014-06-06 22:55:02 +02:00
} else {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
AstNode *range = stmt->children.at(0)->children.at(0).get();
verilog: refactored constant function evaluation Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
2021-01-27 19:21:13 +01:00
if (!range->range_valid) {
if (!must_succeed)
goto finished;
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
range->input_error("Non-constant range\n%s: ... called from here.\n", fcall->loc_string().c_str());
verilog: refactored constant function evaluation Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
2021-01-27 19:21:13 +01:00
}
Import more std:: stuff into Yosys namespace
2015-10-25 19:30:49 +01:00
int offset = min(range->range_left, range->range_right);
Various small fixes (from gcc compiler warnings)
2014-07-23 20:45:27 +02:00
int width = std::abs(range->range_left - range->range_right) + 1;
improved const function support
2014-06-06 22:55:02 +02:00
varinfo_t &v = variables[stmt->children.at(0)->str];
rtlil: represent Const strings as std::string
2024-10-09 19:39:45 +02:00
RTLIL::Const r = stmt->children.at(1)->bitsAsConst(v.val.size());
verilog: fix const func eval with upto variables
2022-01-12 07:51:08 +01:00
for (int i = 0; i < width; i++) {
int index = i + offset - v.offset;
if (v.range_swapped)
index = -index;
rtlil: represent Const strings as std::string
2024-10-09 19:39:45 +02:00
v.val.bits().at(index) = r.at(i);
verilog: fix const func eval with upto variables
2022-01-12 07:51:08 +01:00
}
improved const function support
2014-06-06 22:55:02 +02:00
}
Created basic support for function calls in parameter values
2014-02-14 19:56:44 +01:00
block->children.erase(block->children.begin());
continue;
}
Added support for FOR loops in function calls in parameters
2014-02-14 20:33:22 +01:00
if (stmt->type == AST_FOR)
{
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
stmt->type = AST_WHILE;
log_assert(stmt->children.size() > 2);
auto yoink0 = std::move(stmt->children.at(0));
log_assert(stmt->children.size() > 2);
auto yoink2 = std::move(stmt->children.at(2));
stmt->children.at(3)->children.push_back(std::move(yoink2));
Added support for FOR loops in function calls in parameters
2014-02-14 20:33:22 +01:00
stmt->children.erase(stmt->children.begin() + 2);
stmt->children.erase(stmt->children.begin());
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
block->children.insert(block->children.begin(), std::move(yoink0));
log_assert(stmt->children.size() == 2);
Added support for FOR loops in function calls in parameters
2014-02-14 20:33:22 +01:00
continue;
}
if (stmt->type == AST_WHILE)
{
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto cond = stmt->children.at(0)->clone();
verilog: refactored constant function evaluation Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
2021-01-27 19:21:13 +01:00
if (!cond->replace_variables(variables, fcall, must_succeed))
goto finished;
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
cond->set_in_param_flag(true);
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (cond->simplify(true, 1, -1, false)) { }
Added support for FOR loops in function calls in parameters
2014-02-14 20:33:22 +01:00
verilog: refactored constant function evaluation Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
2021-01-27 19:21:13 +01:00
if (cond->type != AST_CONSTANT) {
if (!must_succeed)
goto finished;
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
stmt->input_error("Non-constant expression in constant function\n%s: ... called from here.\n",
frontend: Make helper functions for printing locations.
2021-02-23 19:22:53 +01:00
fcall->loc_string().c_str());
verilog: refactored constant function evaluation Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
2021-01-27 19:21:13 +01:00
}
Added support for FOR loops in function calls in parameters
2014-02-14 20:33:22 +01:00
if (cond->asBool()) {
block->children.insert(block->children.begin(), stmt->children.at(1)->clone());
} else {
block->children.erase(block->children.begin());
}
continue;
}
Added support for repeat stmt in const functions
2014-06-07 10:47:53 +02:00
if (stmt->type == AST_REPEAT)
{
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto num = stmt->children.at(0)->clone();
verilog: refactored constant function evaluation Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
2021-01-27 19:21:13 +01:00
if (!num->replace_variables(variables, fcall, must_succeed))
goto finished;
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
num->set_in_param_flag(true);
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (num->simplify(true, 1, -1, false)) { }
Added support for repeat stmt in const functions
2014-06-07 10:47:53 +02:00
verilog: refactored constant function evaluation Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
2021-01-27 19:21:13 +01:00
if (num->type != AST_CONSTANT) {
if (!must_succeed)
goto finished;
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
stmt->input_error("Non-constant expression in constant function\n%s: ... called from here.\n",
frontend: Make helper functions for printing locations.
2021-02-23 19:22:53 +01:00
fcall->loc_string().c_str());
verilog: refactored constant function evaluation Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
2021-01-27 19:21:13 +01:00
}
Added support for repeat stmt in const functions
2014-06-07 10:47:53 +02:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
temporary_nodes.push_back(std::move(stmt));
Added support for repeat stmt in const functions
2014-06-07 10:47:53 +02:00
block->children.erase(block->children.begin());
for (int i = 0; i < num->bitsAsConst().as_int(); i++)
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
block->children.insert(block->children.begin(), temporary_nodes.back()->children.at(1)->clone());
Added support for repeat stmt in const functions
2014-06-07 10:47:53 +02:00
continue;
}
Improved support for constant functions
2014-02-16 13:16:38 +01:00
if (stmt->type == AST_CASE)
{
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto expr = stmt->children.at(0)->clone();
verilog: refactored constant function evaluation Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
2021-01-27 19:21:13 +01:00
if (!expr->replace_variables(variables, fcall, must_succeed))
goto finished;
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
expr->set_in_param_flag(true);
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (expr->simplify(true, 1, -1, false)) { }
Improved support for constant functions
2014-02-16 13:16:38 +01:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
AstNode *sel_case = nullptr;
std::unique_ptr<AstNode> sel_case_copy = nullptr;
Improved support for constant functions
2014-02-16 13:16:38 +01:00
for (size_t i = 1; i < stmt->children.size(); i++)
{
bool found_match = false;
Fixed handling of parameters and const functions in casex/casez pattern
2016-04-21 15:31:54 +02:00
log_assert(stmt->children.at(i)->type == AST_COND || stmt->children.at(i)->type == AST_CONDX || stmt->children.at(i)->type == AST_CONDZ);
Improved support for constant functions
2014-02-16 13:16:38 +01:00
if (stmt->children.at(i)->children.front()->type == AST_DEFAULT) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
sel_case = stmt->children.at(i)->children.back().get();
Improved support for constant functions
2014-02-16 13:16:38 +01:00
continue;
}
for (size_t j = 0; j+1 < stmt->children.at(i)->children.size() && !found_match; j++)
{
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto cond = stmt->children.at(i)->children.at(j)->clone();
verilog: refactored constant function evaluation Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
2021-01-27 19:21:13 +01:00
if (!cond->replace_variables(variables, fcall, must_succeed))
goto finished;
Improved support for constant functions
2014-02-16 13:16:38 +01:00
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
cond = std::make_unique<AstNode>(location, AST_EQ, expr->clone(), std::move(cond));
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
cond->set_in_param_flag(true);
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-04-04 22:59:44 +02:00
while (cond->simplify(true, 1, -1, false)) { }
Improved support for constant functions
2014-02-16 13:16:38 +01:00
verilog: refactored constant function evaluation Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
2021-01-27 19:21:13 +01:00
if (cond->type != AST_CONSTANT) {
if (!must_succeed)
goto finished;
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
stmt->input_error("Non-constant expression in constant function\n%s: ... called from here.\n",
frontend: Make helper functions for printing locations.
2021-02-23 19:22:53 +01:00
fcall->loc_string().c_str());
verilog: refactored constant function evaluation Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
2021-01-27 19:21:13 +01:00
}
Improved support for constant functions
2014-02-16 13:16:38 +01:00
found_match = cond->asBool();
}
if (found_match) {
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
sel_case = stmt->children.at(i)->children.back().get();
Improved support for constant functions
2014-02-16 13:16:38 +01:00
break;
}
}
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
if (sel_case)
sel_case_copy = sel_case->clone();
Improved support for constant functions
2014-02-16 13:16:38 +01:00
block->children.erase(block->children.begin());
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
if (sel_case_copy)
block->children.insert(block->children.begin(), std::move(sel_case_copy));
Improved support for constant functions
2014-02-16 13:16:38 +01:00
continue;
}
Added support for FOR loops in function calls in parameters
2014-02-14 20:33:22 +01:00
if (stmt->type == AST_BLOCK)
{
verilog: significant block scoping improvements This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
2021-01-27 19:30:22 +01:00
if (!stmt->str.empty())
stmt->expand_genblock(stmt->str + ".");
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
auto* stmt_leaky = stmt.get();
temporary_nodes.push_back(std::move(stmt));
Added support for FOR loops in function calls in parameters
2014-02-14 20:33:22 +01:00
block->children.erase(block->children.begin());
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
block->children.reserve(block->children.size() + stmt_leaky->children.size());
block->children.insert(block->children.begin(),
std::make_move_iterator(stmt_leaky->children.begin()),
std::make_move_iterator(stmt_leaky->children.end()));
stmt_leaky->children.clear();
ast/simplify: Make in_lvalue/in_param into props of AST nodes Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
2023-04-05 11:00:07 +02:00
block->fixup_hierarchy_flags();
Added support for FOR loops in function calls in parameters
2014-02-14 20:33:22 +01:00
continue;
}
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
// log("C\n");
verilog: refactored constant function evaluation Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
2021-01-27 19:21:13 +01:00
if (!must_succeed)
goto finished;
ast: Move to a new helper method to print input errors It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
2023-04-04 11:53:50 +02:00
stmt->input_error("Unsupported language construct in constant function\n%s: ... called from here.\n",
frontend: Make helper functions for printing locations.
2021-02-23 19:22:53 +01:00
fcall->loc_string().c_str());
Created basic support for function calls in parameter values
2014-02-14 19:56:44 +01:00
log_abort();
}
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
result = AstNode::mkconst_bits(location, variables.at(str).val.to_bits(), variables.at(str).is_signed);
improved ast simplify of const functions
2014-06-06 17:40:45 +02:00
verilog: refactored constant function evaluation Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
2021-01-27 19:21:13 +01:00
finished:
current_scope = backup_scope;
return result;
Created basic support for function calls in parameter values
2014-02-14 19:56:44 +01:00
}
partial rebase of PeterCrozier's enum work onto current master I tried to keep only the enum-related changes, and minimize the diff. (The original commit also had a lot of work done to get typedefs working, but yosys has diverged quite a bit since the 2018-03-09 commit, with a new typedef implementation.) I did not include the import related changes either. Original commit: "Initial implementation of enum, typedef, import. Still a WIP." https://github.com/PeterCrozier/yosys/commit/881833aa738e7404987646ea8076284e911fce3f
2018-03-09 13:47:11 +01:00
void AstNode::allocateDefaultEnumValues()
{
log_assert(type==AST_ENUM);
sv: fix a few struct and enum memory leaks
2021-06-17 21:59:59 +02:00
log_assert(children.size() > 0);
if (children.front()->attributes.count(ID::enum_base_type))
return; // already elaborated
partial rebase of PeterCrozier's enum work onto current master I tried to keep only the enum-related changes, and minimize the diff. (The original commit also had a lot of work done to get typedefs working, but yosys has diverged quite a bit since the 2018-03-09 commit, with a new typedef implementation.) I did not include the import related changes either. Original commit: "Initial implementation of enum, typedef, import. Still a WIP." https://github.com/PeterCrozier/yosys/commit/881833aa738e7404987646ea8076284e911fce3f
2018-03-09 13:47:11 +01:00
int last_enum_int = -1;
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& node : children) {
partial rebase of PeterCrozier's enum work onto current master I tried to keep only the enum-related changes, and minimize the diff. (The original commit also had a lot of work done to get typedefs working, but yosys has diverged quite a bit since the 2018-03-09 commit, with a new typedef implementation.) I did not include the import related changes either. Original commit: "Initial implementation of enum, typedef, import. Still a WIP." https://github.com/PeterCrozier/yosys/commit/881833aa738e7404987646ea8076284e911fce3f
2018-03-09 13:47:11 +01:00
log_assert(node->type==AST_ENUM_ITEM);
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
node->set_attribute(ID::enum_base_type, mkconst_str(node->location, str));
partial rebase of PeterCrozier's enum work onto current master I tried to keep only the enum-related changes, and minimize the diff. (The original commit also had a lot of work done to get typedefs working, but yosys has diverged quite a bit since the 2018-03-09 commit, with a new typedef implementation.) I did not include the import related changes either. Original commit: "Initial implementation of enum, typedef, import. Still a WIP." https://github.com/PeterCrozier/yosys/commit/881833aa738e7404987646ea8076284e911fce3f
2018-03-09 13:47:11 +01:00
for (size_t i = 0; i < node->children.size(); i++) {
switch (node->children[i]->type) {
case AST_NONE:
// replace with auto-incremented constant
ast, read_verilog: unify location types, reduce filename copying
2025-06-18 22:50:46 +02:00
node->children[i] = AstNode::mkconst_int(node->location, ++last_enum_int, true);
partial rebase of PeterCrozier's enum work onto current master I tried to keep only the enum-related changes, and minimize the diff. (The original commit also had a lot of work done to get typedefs working, but yosys has diverged quite a bit since the 2018-03-09 commit, with a new typedef implementation.) I did not include the import related changes either. Original commit: "Initial implementation of enum, typedef, import. Still a WIP." https://github.com/PeterCrozier/yosys/commit/881833aa738e7404987646ea8076284e911fce3f
2018-03-09 13:47:11 +01:00
break;
case AST_CONSTANT:
// explicit constant (or folded expression)
// TODO: can't extend 'x or 'z item
last_enum_int = node->children[i]->integer;
break;
default:
// ignore ranges
break;
}
// TODO: range check
}
}
}
verilog: support recursive functions using ternary expressions This adds a mechanism for marking certain portions of elaboration as occurring within unevaluated ternary branches. To enable elaboration of the overall ternary, this also adds width detection for these unelaborated function calls.
2021-02-12 20:25:34 +01:00
bool AstNode::is_recursive_function() const
{
std::set<const AstNode *> visited;
std::function<bool(const AstNode *node)> visit = [&](const AstNode *node) {
if (visited.count(node))
return node == this;
visited.insert(node);
if (node->type == AST_FCALL) {
auto it = current_scope.find(node->str);
if (it != current_scope.end() && visit(it->second))
return true;
}
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
for (auto& child : node->children) {
if (visit(child.get()))
verilog: support recursive functions using ternary expressions This adds a mechanism for marking certain portions of elaboration as occurring within unevaluated ternary branches. To enable elaboration of the overall ternary, this also adds width detection for these unelaborated function calls.
2021-02-12 20:25:34 +01:00
return true;
}
return false;
};
log_assert(type == AST_FUNCTION);
return visit(this);
}
std::pair<AstNode*, AstNode*> AstNode::get_tern_choice()
{
if (!children[0]->isConst())
return {};
bool found_sure_true = false;
bool found_maybe_true = false;
if (children[0]->type == AST_CONSTANT)
for (auto &bit : children[0]->bits) {
if (bit == RTLIL::State::S1)
found_sure_true = true;
if (bit > RTLIL::State::S1)
found_maybe_true = true;
}
else
found_sure_true = children[0]->asReal(true) != 0;
AstNode *choice = nullptr, *not_choice = nullptr;
if (found_sure_true)
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
choice = children[1].get(), not_choice = children[2].get();
verilog: support recursive functions using ternary expressions This adds a mechanism for marking certain portions of elaboration as occurring within unevaluated ternary branches. To enable elaboration of the overall ternary, this also adds width detection for these unelaborated function calls.
2021-02-12 20:25:34 +01:00
else if (!found_maybe_true)
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-06-16 22:55:24 +02:00
choice = children[2].get(), not_choice = children[1].get();
verilog: support recursive functions using ternary expressions This adds a mechanism for marking certain portions of elaboration as occurring within unevaluated ternary branches. To enable elaboration of the overall ternary, this also adds width detection for these unelaborated function calls.
2021-02-12 20:25:34 +01:00
return {choice, not_choice};
}
verilog: check for module scope identifiers during width detection The recent fix for case expression width detection causes the width of the expressions to be queried before they are simplified. Because the logic supporting module scope identifiers only existed in simplify, looking them up would fail during width detection. This moves the logic to a common helper used in both simplify() and detectSignWidthWorker().
2021-06-05 22:21:09 +02:00
std::string AstNode::try_pop_module_prefix() const
{
AstNode *current_scope_ast = (current_ast_mod == nullptr) ? current_ast : current_ast_mod;
size_t pos = str.find('.', 1);
if (str[0] == '\\' && pos != std::string::npos) {
std::string new_str = "\\" + str.substr(pos + 1);
if (current_scope.count(new_str)) {
std::string prefix = str.substr(0, pos);
auto it = current_scope_ast->attributes.find(ID::hdlname);
ast/simplify: Interpret hdlname w/o expecting backslash
2024-02-13 21:38:41 +01:00
if ((it != current_scope_ast->attributes.end() && it->second->str == prefix.substr(1))
verilog: check for module scope identifiers during width detection The recent fix for case expression width detection causes the width of the expressions to be queried before they are simplified. Because the logic supporting module scope identifiers only existed in simplify, looking them up would fail during width detection. This moves the logic to a common helper used in both simplify() and detectSignWidthWorker().
2021-06-05 22:21:09 +02:00
|| prefix == current_scope_ast->str)
return new_str;
}
}
return str;
}
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
2014-07-31 13:19:47 +02:00
YOSYS_NAMESPACE_END