mirror of https://github.com/YosysHQ/yosys.git
11 lines
150 B
Plaintext
11 lines
150 B
Plaintext
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read_verilog <<EOF
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module bad(
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input in,
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output reg [1:0] out
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);
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assign out = {in, 1'b0};
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endmodule
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EOF
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proc
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write_aiger -vmap /dev/null /dev/null
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