mirror of https://github.com/YosysHQ/yosys.git
40 lines
915 B
Verilog
40 lines
915 B
Verilog
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module wide_op(
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a, b, y, c
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);
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parameter width = 1024;
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// ADD/SUB: 0/4 + (0 unsigned+unsigned, 1 unsigned+signed, 2 signed+unsigned, 3 signed+signed)
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// reserved for MUL: 8
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parameter op = 0;
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localparam ywidth = (op == 8) ? width * 2 : width;
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input[width-1:0] a;
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input[width-1:0] b;
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output [width-1:0] y;
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output c;
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generate
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if (op == 0)
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assign {c, y} = a + b;
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else if (op == 1)
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assign {c, y} = a + $signed(b);
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else if (op == 2)
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assign {c, y} = $signed(a) + b;
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else if (op == 3)
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assign {c, y} = $signed(a) + $signed(b);
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else if (op == 4)
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assign {c, y} = a - b;
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else if (op == 5)
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assign {c, y} = a - $signed(b);
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else if (op == 6)
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assign {c, y} = $signed(a) - b;
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else if (op == 7)
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assign {c, y} = $signed(a) - $signed(b);
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else if (op == 8) begin
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assign c = 0;
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assign y = a * b;
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end
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endgenerate
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endmodule
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