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44fc616fc701d698564d68a7facf210947b8bd9e
yosys
/
tests
/
errors
/
syntax_err13.v
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Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
2018-10-25 02:37:56 +03:00
module
a
#(
p
=
0
)
();
endmodule
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