mirror of
https://github.com/YosysHQ/yosys.git
synced 2026-09-04 11:29:42 +02:00
4 lines
48 B
Verilog
4 lines
48 B
Verilog
|
module a;
|
||
|
|
parameter integer [2:0]x=0;
|
||
|
|
endmodule
|