mirror of
https://github.com/YosysHQ/yosys.git
synced 2026-09-04 11:29:42 +02:00
5 lines
35 B
Verilog
5 lines
35 B
Verilog
|
module a;
|
||
|
|
input x[2:0];
|
||
|
|
endmodule
|
||
|
|
|