mirror of
https://github.com/YosysHQ/yosys.git
synced 2026-09-05 19:36:55 +02:00
4 lines
34 B
Verilog
4 lines
34 B
Verilog
|
module a;
|
||
|
|
input x[2:0];
|
||
|
|
endmodule
|