mirror of https://github.com/YosysHQ/yosys.git
14 lines
241 B
Plaintext
14 lines
241 B
Plaintext
|
read_verilog -icells <<EOF
|
||
|
|
module top(input wire [2:0] a, output wire [2:0] y);
|
||
|
|
\$buf #(.WIDTH(3)) b(.A(a), .Y(y));
|
||
|
|
endmodule
|
||
|
|
EOF
|
||
|
|
design -save save
|
||
|
|
|
||
|
|
opt_clean
|
||
|
|
select -assert-none t:$buf
|
||
|
|
|
||
|
|
design -load save
|
||
|
|
techmap
|
||
|
|
select -assert-none t:$buf
|