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17 lines
316 B
Systemverilog
17 lines
316 B
Systemverilog
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import package_import_specific::DATA_WIDTH;
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import package_import_specific::IDLE;
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module package_import_specific_module;
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logic [DATA_WIDTH-1:0] data;
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logic [3:0] addr;
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logic [2:0] state;
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always_comb begin
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case (state)
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IDLE: data = 8'h00;
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default: data = 8'hFF;
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endcase
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end
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endmodule
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