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10 lines
256 B
Plaintext
10 lines
256 B
Plaintext
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# Regression test for issue #5734: muxpack crash when $logic_not / $eq / $reduce_or
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# has Y port width > 1 (e.g. boolean result assigned to a wide wire).
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read_verilog <<EOT
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module top(input b, output [18:0] h);
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assign h = ~|b;
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endmodule
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EOT
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proc
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muxpack
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