mirror of https://github.com/YosysHQ/yosys.git
15 lines
201 B
Plaintext
15 lines
201 B
Plaintext
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# Test debug -on/-off modes
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design -reset
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read_verilog <<EOT
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module top(input a, input b, output y);
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assign y = a & b;
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endmodule
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EOT
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debug -on
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hierarchy
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select -assert-count 1 t:$and
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debug -off
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