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2c96ecc5f7d88cfd8dbddc3e5f45fb0a2a9bb6d3
yosys
/
tests
/
errors
/
syntax_err06.v
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Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
2018-10-25 02:37:56 +03:00
module
a
;
initial
begin
:
label1
end
:
label2
endmodule
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