yosys/tests/techmap/dfflibmap_wide.ys

mirror of https://github.com/YosysHQ/yosys.git
read_verilog ../sim/dff.v
proc
logger -expect error "not supported" 1
dfflibmap -liberty dfflibmap.lib
logger -check-expected
dfflibmap: error on wide registers in design 2026-07-27 22:24:28 +02:00			`read_verilog ../sim/dff.v`
			`proc`
			`logger -expect error "not supported" 1`
			`dfflibmap -liberty dfflibmap.lib`
liberty: cleanup 2026-07-30 16:44:12 +02:00			`logger -check-expected`