mirror of https://github.com/YosysHQ/yosys.git
483 lines
18 KiB
Python
483 lines
18 KiB
Python
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import time
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import logging
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import yaml
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import os
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import re
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import subprocess
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from datetime import timedelta
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from datetime import datetime
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import threading
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import csv
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# Constants
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CLK_TYPE_RISE = "RISING"
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CLK_TYPE_FALL = "FALLING"
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RST_TYPE_SYNC = "SYNCHRONOUS"
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RST_TYPE_ASYNC = "ASYNCHRONOUS"
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RST_POLARITY_L = "ACTIVE-LOW"
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RST_POLARITY_H = "ACTIVE-HIGH"
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EVENT_TYPE_LOAD = "LOAD"
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EVENT_TYPE_ADD = "ADD"
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EVENT_TYPE_SUB = "SUBTRACT"
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EVENT_TYPE_SR = "SHIFT-RIGHT"
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EVENT_TYPE_SL = "SHIFT-LEFT"
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# Class of an mini pin table
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class PcounterIpTemplateGenerator:
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def __init__(self):
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# Constants
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self.__CLK_TYPES_ = [CLK_TYPE_RISE, CLK_TYPE_FALL]
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self.__RST_TYPES_ = [RST_TYPE_SYNC, RST_TYPE_ASYNC]
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self.__RST_POLARITIES_ = [RST_POLARITY_L, RST_POLARITY_H]
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self.__EVENT_TYPES_ = [
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EVENT_TYPE_LOAD,
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EVENT_TYPE_ADD,
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EVENT_TYPE_SUB,
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EVENT_TYPE_SR,
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EVENT_TYPE_SL,
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]
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self.__MAX_DATA_SIZE_ = 32
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self.__CCB_POSTFIX_ = "_ccb"
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# Internal switches
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self.__include_q_ = False
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# Create a new row
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def clock_types(self):
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return self.__CLK_TYPES_
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def reset_types(self):
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return self.__RST_TYPES_
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def reset_polarities(self):
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return self.__RST_POLARITIES_
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def event_types(self):
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return self.__EVENT_TYPES_
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def data_sizes(self):
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return range(1, self.__MAX_DATA_SIZE_ + 1)
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def max_data_size(self):
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return self.__MAX_DATA_SIZE_
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def __verilog_clock_edge(self, edge_type):
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if edge_type == CLK_TYPE_RISE:
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return "posedge"
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elif edge_type == CLK_TYPE_FALL:
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return "negedge"
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else:
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raise Exception(f"Invalid clock type '{edge_type}'. Expect {self.__CLK_TYPES_}\n")
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def __verilog_reset_edge(self, edge_type):
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if edge_type == RST_POLARITY_H:
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return "posedge"
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elif edge_type == RST_POLARITY_L:
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return "negedge"
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else:
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raise Exception(f"Invalid reset type '{edge_type}'. Expect {self.__RST_POLARITIES_}\n")
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def __verilog_reset_polarity(self, polarity_type):
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if polarity_type == RST_POLARITY_L:
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return "~"
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elif polarity_type == RST_POLARITY_H:
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return ""
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else:
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raise Exception(
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f"Invalid reset type '{polarity_type}'. Expect {self.__RST_POLARITIES}\n"
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)
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def __verilog_event_op_ccb(self, event_type):
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if event_type == EVENT_TYPE_LOAD:
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return "ccb_load_val_i"
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elif event_type == EVENT_TYPE_ADD:
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return "q_o + ccb_load_val_i"
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elif event_type == EVENT_TYPE_SUB:
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return "q_o - ccb_load_val_i"
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elif event_type == EVENT_TYPE_SL:
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return "q_o << ccb_load_val_i"
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elif event_type == EVENT_TYPE_SR:
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return "q_o >> ccb_load_val_i"
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else:
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raise Exception(f"Invalid event type '{event_type}'. Expect {self.__EVENT_TYPES_}\n")
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def __verilog_event_op(self, event_type):
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if event_type == EVENT_TYPE_LOAD:
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return "LOAD_VAL"
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elif event_type == EVENT_TYPE_ADD:
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return "q_o + LOAD_VAL"
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elif event_type == EVENT_TYPE_SUB:
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return "q_o - LOAD_VAL"
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elif event_type == EVENT_TYPE_SL:
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return "q_o << LOAD_VAL"
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elif event_type == EVENT_TYPE_SR:
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return "q_o >> LOAD_VAL"
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else:
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raise Exception(f"Invalid event type '{event_type}'. Expect {self.__EVENT_TYPES_}\n")
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def __clock_type_str(self, edge_type):
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if edge_type == CLK_TYPE_RISE:
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return "clkp"
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elif edge_type == CLK_TYPE_FALL:
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return "clkn"
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else:
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raise Exception(f"Invalid clock type '{edge_type}'. Expect {self.__CLK_TYPES_}\n")
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def __reset_type_str(self, edge_type, polarity_type):
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ret = ""
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if edge_type == RST_TYPE_ASYNC:
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ret = "arst"
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elif edge_type == RST_TYPE_SYNC:
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ret = "srst"
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else:
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raise Exception(f"Invalid reset type '{edge_type}'. Expect {self.__RST_TYPES_}\n")
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if polarity_type == RST_POLARITY_L:
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ret += "n"
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elif polarity_type == RST_POLARITY_H:
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ret += "p"
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else:
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raise Exception(
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f"Invalid reset type '{polarity_type}'. Expect {self.__RST_POLARITIES}\n"
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)
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return ret
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def __event_type_str(self, event_type):
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if event_type == EVENT_TYPE_LOAD:
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return "load"
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elif event_type == EVENT_TYPE_ADD:
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return "add"
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elif event_type == EVENT_TYPE_SUB:
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return "sub"
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elif event_type == EVENT_TYPE_SL:
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return "sl"
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elif event_type == EVENT_TYPE_SR:
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return "sr"
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else:
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raise Exception(f"Invalid event type '{event_type}'. Expect {self.__EVENT_TYPES_}\n")
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def ccb_ip_template_name(self, c_type, r_type, r_polar, e_type):
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return (
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"pcounterN_"
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+ self.__clock_type_str(c_type)
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+ "_"
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+ self.__reset_type_str(r_type, r_polar)
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+ "_"
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+ self.__event_type_str(e_type)
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+ self.__CCB_POSTFIX_
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)
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def ip_template_name(self, c_type, r_type, r_polar, e_type):
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return (
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"pcounterN_"
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+ self.__clock_type_str(c_type)
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+ "_"
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+ self.__reset_type_str(r_type, r_polar)
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+ "_"
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+ self.__event_type_str(e_type)
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)
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def ip_name(self, c_type, r_type, r_polar, e_type, d_size):
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return (
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"pcounter"
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+ str(d_size)
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+ "_"
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+ self.__clock_type_str(c_type)
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+ "_"
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+ self.__reset_type_str(r_type, r_polar)
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+ "_"
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+ self.__event_type_str(e_type)
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)
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def ccb_ip_name(self, c_type, r_type, r_polar, e_type, d_size):
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return (
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"pcounter"
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+ str(d_size)
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+ "_"
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+ self.__clock_type_str(c_type)
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+ "_"
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+ self.__reset_type_str(r_type, r_polar)
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+ "_"
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+ self.__event_type_str(e_type)
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+ self.__CCB_POSTFIX_
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)
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def write_ccb_ip_template(self, f0, c_type, r_type, r_polar, e_type):
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f0.write("//-------------------------------------------------\n\n")
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f0.write(
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"// Template of Programmable counter to be counting up or down as well as paused\n\n"
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)
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f0.write(f"// triggered by {c_type.lower()} edge clock\n\n")
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f0.write(f"// with {r_type.lower()} {r_polar.lower()} reset\n\n")
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f0.write(f"// Capable of {e_type.lower()} values from inputs\n\n")
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f0.write("`default_nettype none\n\n")
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f0.write(f"module {self.ccb_ip_template_name(c_type, r_type, r_polar, e_type)} #(\n")
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f0.write(f" parameter integer DATA_WIDTH = {self.__MAX_DATA_SIZE_}\n")
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f0.write(")(\n")
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f0.write(" input clk_i,\n")
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f0.write(" input rst_i,\n")
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f0.write(" input up_down_i,\n")
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f0.write(" input event_i,\n")
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f0.write(" input enable_i,\n")
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f0.write(" input [0 : DATA_WIDTH - 1] ccb_match0_ref_i,\n")
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f0.write(" input [0 : DATA_WIDTH - 1] ccb_match1_ref_i,\n")
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f0.write(" input [0 : DATA_WIDTH - 1] ccb_load_val_i,\n")
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f0.write(" output match0_o,\n")
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f0.write(" output match1_o,\n")
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f0.write(" output zero_o,\n")
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f0.write(" output [0 : DATA_WIDTH - 1] q_o\n")
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f0.write(");\n")
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f0.write(" reg [0 : DATA_WIDTH - 1] q_o;\n")
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if r_type == RST_TYPE_ASYNC:
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f0.write(
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f" always@({self.__verilog_clock_edge(c_type)} clk_i or {self.__verilog_reset_edge(r_polar)} rst_i) \n"
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)
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elif r_type == RST_TYPE_SYNC:
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f0.write(f" always@({self.__verilog_clock_edge(c_type)} clk_i) \n")
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else:
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raise Exception(f"Invalid reset type '{edge_type}'. Expect {self.__RST_TYPES_}\n")
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f0.write(" begin\n")
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f0.write(
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f" if ({self.__verilog_reset_polarity(r_polar)}rst_i) //Set Counter to Zero\n"
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)
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f0.write(" q_o <= 0;\n")
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f0.write(" else if(event_i)\n")
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f0.write(f" q_o <= {self.__verilog_event_op_ccb(e_type)};\n")
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f0.write(" else if (~enable_i)\n")
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f0.write(" q_o <= q_o; // pause\n")
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f0.write(" else if(up_down_i) //count down\n")
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f0.write(" q_o <= q_o - 1;\n")
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f0.write(" else //count up\n")
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f0.write(" q_o <= q_o + 1;\n")
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f0.write(" end\n")
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f0.write(" assign zero_o = (q_o == 0) ? 1 : 0;\n")
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f0.write(" assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0;\n")
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f0.write(" assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0;\n")
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f0.write("endmodule\n")
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f0.write("`default_nettype wire\n")
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def write_ip_template(self, f0, c_type, r_type, r_polar, e_type):
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f0.write("//-------------------------------------------------\n\n")
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f0.write(
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"// Template of Programmable counter to be counting up or down as well as paused\n\n"
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)
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f0.write(f"// triggered by {c_type.lower()} edge clock\n\n")
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f0.write(f"// with {r_type.lower()} {r_polar.lower()} reset\n\n")
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f0.write(f"// Capable of {e_type.lower()} values from inputs\n\n")
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f0.write("`default_nettype none\n\n")
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f0.write(f"module {self.ip_template_name(c_type, r_type, r_polar, e_type)} #(\n")
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f0.write(f" parameter integer DATA_WIDTH = {self.__MAX_DATA_SIZE_},\n")
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f0.write(" parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}},\n")
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f0.write(" parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}},\n")
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f0.write(" parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}}\n")
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f0.write(")(\n")
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f0.write(" input clk_i,\n")
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f0.write(" input rst_i,\n")
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f0.write(" input up_down_i,\n")
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f0.write(" input event_i,\n")
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f0.write(" input enable_i,\n")
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f0.write(" output match0_o,\n")
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f0.write(" output match1_o,\n")
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f0.write(" output zero_o")
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if self.__include_q_:
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f0.write(",\n")
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f0.write(" output [0 : DATA_WIDTH - 1] q_o\n")
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f0.write(");\n")
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f0.write(" reg [0 : DATA_WIDTH - 1] q_o;\n")
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if r_type == RST_TYPE_ASYNC:
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f0.write(
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f" always@({self.__verilog_clock_edge(c_type)} clk_i or {self.__verilog_reset_edge(r_polar)} rst_i) \n"
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)
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elif r_type == RST_TYPE_SYNC:
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f0.write(f" always@({self.__verilog_clock_edge(c_type)} clk_i) \n")
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else:
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raise Exception(f"Invalid reset type '{edge_type}'. Expect {self.__RST_TYPES_}\n")
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f0.write(" begin\n")
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f0.write(
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f" if ({self.__verilog_reset_polarity(r_polar)}rst_i) //Set Counter to Zero\n"
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)
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f0.write(" q_o <= 0;\n")
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f0.write(" else if(event_i)\n")
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f0.write(f" q_o <= {self.__verilog_event_op(e_type)};\n")
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f0.write(" else if (~enable_i)\n")
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f0.write(" q_o <= q_o; // pause\n")
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f0.write(" else if(up_down_i) //count down\n")
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f0.write(" q_o <= q_o - 1;\n")
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f0.write(" else //count up\n")
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f0.write(" q_o <= q_o + 1;\n")
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f0.write(" end\n")
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f0.write(" assign zero_o = (q_o == 0) ? 1 : 0;\n")
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f0.write(" assign match0_o = (q_o == MATCH0_REF) ? 1 : 0;\n")
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f0.write(" assign match1_o = (q_o == MATCH1_REF) ? 1 : 0;\n")
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f0.write("endmodule\n")
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f0.write("`default_nettype wire\n")
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def write_ccb_ip(self, f0, c_type, r_type, r_polar, e_type, d_size, require_padding=False):
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d_msb = d_size - 1
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||
|
|
f0.write("`default_nettype none\n\n")
|
||
|
|
f0.write(f"module {self.ccb_ip_name(c_type, r_type, r_polar, e_type, d_size)} # (\n")
|
||
|
|
f0.write(" // Location constraints\n")
|
||
|
|
f0.write(" parameter FPGA_LOC_X = 0,\n")
|
||
|
|
f0.write(" parameter FPGA_LOC_Y = 0,\n")
|
||
|
|
f0.write(" parameter FPGA_LOC_Z = 0)(\n")
|
||
|
|
f0.write(" input clk_i,\n")
|
||
|
|
f0.write(" input rst_i,\n")
|
||
|
|
f0.write(" input up_down_i,\n")
|
||
|
|
f0.write(" input event_i,\n")
|
||
|
|
f0.write(" input enable_i,\n")
|
||
|
|
f0.write(f" input [0 : {d_msb}] ccb_match0_ref_i,\n")
|
||
|
|
f0.write(f" input [0 : {d_msb}] ccb_match1_ref_i,\n")
|
||
|
|
f0.write(f" input [0 : {d_msb}] ccb_load_val_i,\n")
|
||
|
|
f0.write(" output match0_o,\n")
|
||
|
|
f0.write(" output match1_o,\n")
|
||
|
|
f0.write(" output zero_o,\n")
|
||
|
|
f0.write(f" output [0 : {d_msb}] q_o\n")
|
||
|
|
f0.write(");\n")
|
||
|
|
|
||
|
|
# Local wire
|
||
|
|
padding_size = self.__MAX_DATA_SIZE_ - d_size
|
||
|
|
# Padding
|
||
|
|
# q_padding_str = "q_o"
|
||
|
|
# if require_padding:
|
||
|
|
# if padding_size:
|
||
|
|
# q_padding_str = "{ q_o, {" + str(padding_size) + "{1'b0}} }"
|
||
|
|
# f0.write(f"wire [0: {self.__MAX_DATA_SIZE_ - 1}] q_wire;\n")
|
||
|
|
# f0.write(f"assign q_wire = {q_padding_str};\n")
|
||
|
|
# else:
|
||
|
|
# f0.write(f"wire [0: {d_size - 1}] q_wire;\n")
|
||
|
|
# f0.write(f"assign q_wire = q_o;\n")
|
||
|
|
|
||
|
|
f0.write(f" {self.ccb_ip_template_name(c_type, r_type, r_polar, e_type)} #(\n")
|
||
|
|
if require_padding:
|
||
|
|
f0.write(f" .DATA_WIDTH({self.__MAX_DATA_SIZE_})\n")
|
||
|
|
else:
|
||
|
|
f0.write(f" .DATA_WIDTH({d_size})\n")
|
||
|
|
|
||
|
|
load_val_padding_str = "ccb_load_val_i"
|
||
|
|
if require_padding:
|
||
|
|
if padding_size:
|
||
|
|
load_val_padding_str = "{ ccb_load_val_i, {" + str(padding_size) + "{1'b0}} }"
|
||
|
|
|
||
|
|
match0_padding_str = "ccb_match0_ref_i"
|
||
|
|
if require_padding:
|
||
|
|
if padding_size:
|
||
|
|
match0_padding_str = "{ ccb_match0_ref_i, {" + str(padding_size) + "{1'b0}} }"
|
||
|
|
|
||
|
|
match1_padding_str = "ccb_match1_ref_i"
|
||
|
|
if require_padding:
|
||
|
|
if padding_size:
|
||
|
|
match1_padding_str = "{ ccb_match1_ref_i, {" + str(padding_size) + "{1'b0}} }"
|
||
|
|
|
||
|
|
f0.write(" ) core (\n")
|
||
|
|
f0.write(" .clk_i(clk_i),\n")
|
||
|
|
f0.write(" .rst_i(rst_i),\n")
|
||
|
|
f0.write(" .up_down_i(up_down_i),\n")
|
||
|
|
f0.write(" .event_i(event_i),\n")
|
||
|
|
f0.write(" .enable_i(enable_i),\n")
|
||
|
|
f0.write(f" .ccb_load_val_i({load_val_padding_str}),\n")
|
||
|
|
f0.write(f" .ccb_match0_ref_i({match0_padding_str}),\n")
|
||
|
|
f0.write(f" .ccb_match1_ref_i({match1_padding_str}),\n")
|
||
|
|
f0.write(" .match0_o(match0_o),\n")
|
||
|
|
f0.write(" .match1_o(match1_o),\n")
|
||
|
|
f0.write(" .zero_o(zero_o),\n")
|
||
|
|
f0.write(f" .q_o(q_o)\n")
|
||
|
|
|
||
|
|
f0.write(" );\n")
|
||
|
|
f0.write("endmodule\n")
|
||
|
|
f0.write("`default_nettype wire\n")
|
||
|
|
|
||
|
|
def write_ip(self, f0, c_type, r_type, r_polar, e_type, d_size, require_padding=False):
|
||
|
|
d_msb = d_size - 1
|
||
|
|
f0.write("`default_nettype none\n\n")
|
||
|
|
f0.write(f"module {self.ip_name(c_type, r_type, r_polar, e_type, d_size)} #(\n")
|
||
|
|
f0.write(" // Location constraints\n")
|
||
|
|
f0.write(" parameter FPGA_LOC_X = 0,\n")
|
||
|
|
f0.write(" parameter FPGA_LOC_Y = 0,\n")
|
||
|
|
f0.write(" parameter FPGA_LOC_Z = 0,\n")
|
||
|
|
f0.write(" parameter [0 : " + str(d_msb) + "] LOAD_VAL = {" + str(d_size) + "{1'b0}},\n")
|
||
|
|
f0.write(" parameter [0 : " + str(d_msb) + "] MATCH0_REF = {" + str(d_size) + "{1'b0}},\n")
|
||
|
|
f0.write(" parameter [0 : " + str(d_msb) + "] MATCH1_REF = {" + str(d_size) + "{1'b0}}\n")
|
||
|
|
f0.write(")(\n")
|
||
|
|
f0.write(" input clk_i,\n")
|
||
|
|
f0.write(" input rst_i,\n")
|
||
|
|
f0.write(" input up_down_i,\n")
|
||
|
|
f0.write(" input event_i,\n")
|
||
|
|
f0.write(" input enable_i,\n")
|
||
|
|
f0.write(" output match0_o,\n")
|
||
|
|
f0.write(" output match1_o,\n")
|
||
|
|
f0.write(" output zero_o")
|
||
|
|
|
||
|
|
if self.__include_q_:
|
||
|
|
f0.write(",\n")
|
||
|
|
f0.write(f" output [0 : {d_msb}] q_o\n")
|
||
|
|
else:
|
||
|
|
f0.write("\n")
|
||
|
|
|
||
|
|
f0.write(");\n")
|
||
|
|
|
||
|
|
# Local wire
|
||
|
|
padding_size = self.__MAX_DATA_SIZE_ - d_size
|
||
|
|
# if self.__include_q_:
|
||
|
|
# q_padding_str = "q_o"
|
||
|
|
# if require_padding:
|
||
|
|
# if padding_size:
|
||
|
|
# q_padding_str = "{ q_o, {" + str(padding_size) + "{1'b0}} }"
|
||
|
|
# f0.write(f"wire [0: {self.__MAX_DATA_SIZE_ - 1}] q_wire;\n")
|
||
|
|
# f0.write(f"assign q_wire = {q_padding_str};\n")
|
||
|
|
# else:
|
||
|
|
# f0.write(f"wire [0: {d_size - 1}] q_wire;\n")
|
||
|
|
# f0.write(f"assign q_wire = {q_padding_str};\n")
|
||
|
|
|
||
|
|
f0.write(f" {self.ip_template_name(c_type, r_type, r_polar, e_type)} #(\n")
|
||
|
|
if require_padding:
|
||
|
|
f0.write(f" .DATA_WIDTH({self.__MAX_DATA_SIZE_})\n")
|
||
|
|
else:
|
||
|
|
f0.write(f" .DATA_WIDTH({d_size}),\n")
|
||
|
|
|
||
|
|
load_val_padding_str = "LOAD_VAL"
|
||
|
|
if require_padding:
|
||
|
|
if padding_size:
|
||
|
|
load_val_padding_str = "{ LOAD_VAL, {" + str(padding_size) + "{1'b0}} }"
|
||
|
|
f0.write(f" .LOAD_VAL({load_val_padding_str}),\n")
|
||
|
|
|
||
|
|
match0_padding_str = "MATCH0_REF"
|
||
|
|
if require_padding:
|
||
|
|
if padding_size:
|
||
|
|
match0_padding_str = "{ MATCH0_REF, {" + str(padding_size) + "{1'b0}} }"
|
||
|
|
f0.write(f" .MATCH0_REF({match0_padding_str}),\n")
|
||
|
|
|
||
|
|
match1_padding_str = "MATCH1_REF"
|
||
|
|
if require_padding:
|
||
|
|
if padding_size:
|
||
|
|
match1_padding_str = "{ MATCH1_REF, {" + str(padding_size) + "{1'b0}} }"
|
||
|
|
f0.write(f" .MATCH1_REF({match1_padding_str})\n")
|
||
|
|
|
||
|
|
f0.write(" ) core (\n")
|
||
|
|
f0.write(" .clk_i(clk_i),\n")
|
||
|
|
f0.write(" .rst_i(rst_i),\n")
|
||
|
|
f0.write(" .up_down_i(up_down_i),\n")
|
||
|
|
f0.write(" .event_i(event_i),\n")
|
||
|
|
f0.write(" .enable_i(enable_i),\n")
|
||
|
|
f0.write(" .match0_o(match0_o),\n")
|
||
|
|
f0.write(" .match1_o(match1_o),\n")
|
||
|
|
f0.write(" .zero_o(zero_o)")
|
||
|
|
|
||
|
|
if self.__include_q_:
|
||
|
|
f0.write(",\n")
|
||
|
|
f0.write(f" .q_o(q_o)\n")
|
||
|
|
else:
|
||
|
|
f0.write("\n")
|
||
|
|
|
||
|
|
f0.write(" );\n")
|
||
|
|
f0.write("endmodule\n")
|
||
|
|
f0.write("`default_nettype wire\n")
|
||
|
|
|
||
|
|
# Clear all the data
|
||
|
|
def clear(self):
|
||
|
|
self.__init__()
|