mirror of https://github.com/YosysHQ/yosys.git
16 lines
317 B
Verilog
16 lines
317 B
Verilog
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//---------------------------------------
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// 1-bit adder
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//---------------------------------------
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(* abc9_box, lib_whitebox *)
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module _fpga_adder(
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output sumout,
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output cout,
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input a,
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input b,
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input cin
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);
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assign sumout = a ^ b ^ cin;
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assign cout = (a & b) | ((a | b) & cin);
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endmodule
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