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8 lines
240 B
Verilog
8 lines
240 B
Verilog
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//-------------------------------------------------
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// Include all the primitives
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//-------------------------------------------------
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`include "cell_sim_arith.v"
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`include "cell_sim_dsp.v"
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`include "cell_sim_bram.v"
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`include "cell_sim_ff.v"
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