mirror of https://github.com/YosysHQ/yosys.git
29 lines
840 B
Verilog
29 lines
840 B
Verilog
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///////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// File name: define.v
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// Descriptions: This file is the opcode for ccb tile instructions
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// Author: Yihong
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// Date: 2025/8/14
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// Revision: 0.0.1
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// Revision History:
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// V0.0.1 - 2025/8/14 initial release
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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//Operations
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`define ADD 4'b1000
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`define SUB 4'b1001
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`define PUSH 4'b1010
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`define PULL 4'b1011
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`define MOV 4'b1100
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`define MOV_T1 4'b1101
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`define MOV_T2 4'b1110
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`define INTR 4'b1111
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`define NA 10'h000
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// SRC/DES
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`define R0 3'b000
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`define R1 3'b001
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`define R2 3'b010
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`define R3 3'b011
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`define C0 3'b100
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`define C1 3'b101
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`define C2 3'b110
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