mirror of https://github.com/YosysHQ/yosys.git
16 lines
194 B
Plaintext
16 lines
194 B
Plaintext
|
read_rtlil << EOT
|
||
|
|
module \top
|
||
|
|
wire \sig
|
||
|
|
wire \val
|
||
|
|
process $2
|
||
|
|
attribute \full_case 1
|
||
|
|
switch \sig
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end
|
||
|
|
EOT
|
||
|
|
|
||
|
|
write_verilog bug5572.v
|
||
|
|
design -reset
|
||
|
|
read_verilog bug5572.v
|