mirror of https://github.com/YosysHQ/yosys.git
11 lines
194 B
Verilog
11 lines
194 B
Verilog
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module json_param_defaults #(
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parameter WIDTH = 8,
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parameter SIGNED = 1
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) (
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input [WIDTH-1:0] a,
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output [WIDTH-1:0] y
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);
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wire [WIDTH-1:0] y_int = a << SIGNED;
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assign y = y_int;
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endmodule
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