2026-01-29 11:42:23 +01:00
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from pathlib import Path
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2026-01-18 11:11:09 +01:00
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from pyosys import libyosys as ys
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__file_dir__ = Path(__file__).absolute().parent
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2026-01-29 11:42:23 +01:00
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add_sub = __file_dir__.parent / "arch" / "common" / "add_sub.v"
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base = ys.Design()
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base.run_pass(["read_verilog", str(add_sub)])
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base.run_pass("hierarchy -top top")
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base.run_pass(["proc"])
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base.run_pass("equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5")
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2026-01-18 11:11:09 +01:00
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2026-01-29 11:42:23 +01:00
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postopt = ys.Design()
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postopt.run_pass("design -load postopt")
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postopt.run_pass(["cd", "top"])
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postopt.run_pass("select -assert-min 25 t:LUT4")
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postopt.run_pass("select -assert-max 26 t:LUT4")
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postopt.run_pass(["select", "-assert-count", "10", "t:PFUMX"])
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postopt.run_pass(["select", "-assert-count", "6", "t:L6MUX21"])
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postopt.run_pass("select -assert-none t:LUT4 t:PFUMX t:L6MUX21 %% t:* %D")
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