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18bcd0b499a30c4b1c25afa04f092a81546a67c8
yosys
/
tests
/
errors
/
syntax_err05.v
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Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
2018-10-25 02:37:56 +03:00
module
a
;
input
x
[
2
:
0
];
endmodule
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