mirror of https://github.com/YosysHQ/yosys.git
87 lines
2.9 KiB
C++
87 lines
2.9 KiB
C++
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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* 2026 Stan Lee <stan@silimate.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct RegRenamePass : public Pass {
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RegRenamePass() : Pass("reg_rename", "renames register output wires to the correct register name") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" reg_rename\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing reg_rename pass\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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// No options currently. When adding in the future make sure to update docstring with [options]
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break;
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}
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extra_args(args, argidx, design);
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uint32_t count = 0;
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uint32_t moduleCount = design->selected_modules().size();
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for (auto module : design->selected_modules()) {
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for (auto cell : module->selected_cells()) {
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// Rename the register output wire to the register name with
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// "_reg" suffix removed.
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if (cell->name.ends_with("_reg")) {
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IdString registerName = cell->name.substr(0, cell->name.size() - 4);
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for (auto conn : cell->connections()) {
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if (conn.first == ID::Q && conn.second.is_wire()) {
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Wire *wire = conn.second.as_wire();
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// Skip if this wire is a module port (input/output)
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if (wire->port_input || wire->port_output) {
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log("Skipping port wire %s in register renaming for cell %s in module %s\n",
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wire->name.c_str(), log_id(cell), log_id(module));
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continue;
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}
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// Skip if we already renamed the wire
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if (wire->name == registerName) {
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continue;
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}
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// Rename register
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log("Renaming register wire %s to %s for cell %s in module %s\n",
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wire->name.c_str(), registerName.c_str(), log_id(cell), log_id(module));
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module->rename(wire, registerName);
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count++;
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}
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}
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}
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}
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}
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log("Renamed %d registers in %d modules\n", count, moduleCount);
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log_flush();
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}
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} RegRenamePass;
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PRIVATE_NAMESPACE_END
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