yosys/tests/verilog/wire_and_var.ys

logger -expect warning 'wire .\\wire_1. is assigned in a block' 1
logger -expect warning 'reg .\\reg_2. is assigned in a continuous assignment' 1

logger -expect warning 'reg .\\var_reg_2. is assigned in a continuous assignment' 1

logger -expect warning 'wire .\\wire_logic_1. is assigned in a block' 1
logger -expect warning 'wire .\\wire_integer_1. is assigned in a block' 1

read_verilog -sv wire_and_var.sv
Tests: Prefer single quotes for regex Replaces double quotes on problematic regex strings (mostly ones that have escape sequences that are easier to preserve in single quotes). Necessitates also changing single quotes to `.`, i.e match any. For some (mostly ones that only have a single escaped character, or were using `\.` to match a literal fullstop) keep the double quotes and fix the regex instead. 2025-10-06 03:22:18 +02:00			`logger -expect warning 'wire .\\wire_1. is assigned in a block' 1`
			`logger -expect warning 'reg .\\reg_2. is assigned in a continuous assignment' 1`
sv: fix support wire and var data type modifiers 2021-01-20 17:15:48 +01:00
Tests: Prefer single quotes for regex Replaces double quotes on problematic regex strings (mostly ones that have escape sequences that are easier to preserve in single quotes). Necessitates also changing single quotes to `.`, i.e match any. For some (mostly ones that only have a single escaped character, or were using `\.` to match a literal fullstop) keep the double quotes and fix the regex instead. 2025-10-06 03:22:18 +02:00			`logger -expect warning 'reg .\\var_reg_2. is assigned in a continuous assignment' 1`
sv: fix support wire and var data type modifiers 2021-01-20 17:15:48 +01:00
Tests: Prefer single quotes for regex Replaces double quotes on problematic regex strings (mostly ones that have escape sequences that are easier to preserve in single quotes). Necessitates also changing single quotes to `.`, i.e match any. For some (mostly ones that only have a single escaped character, or were using `\.` to match a literal fullstop) keep the double quotes and fix the regex instead. 2025-10-06 03:22:18 +02:00			`logger -expect warning 'wire .\\wire_logic_1. is assigned in a block' 1`
			`logger -expect warning 'wire .\\wire_integer_1. is assigned in a block' 1`
sv: fix support wire and var data type modifiers 2021-01-20 17:15:48 +01:00
			`read_verilog -sv wire_and_var.sv`