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yosys/tests/verilog/macro_unapplied.ys

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verilog: error on macro invocations with missing argument lists This would previously complain about an undefined internal macro if the unapplied macro had not already been used. If it had, it would incorrectly use the arguments from the previous invocation.
2021-02-18 18:04:02 +01:00
logger -expect-no-warnings
read_verilog -sv <<EOT
`define MACRO(a = 1, b = 2) initial $display("MACRO(a = %d, b = %d)", a, b)
module top;
`MACRO();
endmodule
EOT
design -reset
Tests: Prefer single quotes for regex Replaces double quotes on problematic regex strings (mostly ones that have escape sequences that are easier to preserve in single quotes). Necessitates also changing single quotes to `.`, i.e match any. For some (mostly ones that only have a single escaped character, or were using `\.` to match a literal fullstop) keep the double quotes and fix the regex instead.
2025-10-06 03:22:18 +02:00
logger -expect error "Expected to find '\\(' to begin macro arguments for 'MACRO', but instead found ';'" 1
verilog: error on macro invocations with missing argument lists This would previously complain about an undefined internal macro if the unapplied macro had not already been used. If it had, it would incorrectly use the arguments from the previous invocation.
2021-02-18 18:04:02 +01:00
read_verilog -sv <<EOT
`define MACRO(a = 1, b = 2) initial $display("MACRO(a = %d, b = %d)", a, b)
module top;
`MACRO;
endmodule
EOT