yosys/tests/verilog/gen_block_end_label_wrong.ys

logger -expect error 'Begin label \(correct_name\) and end label \(incorrect_name\) don.t match\.' 1
read_verilog -sv <<EOF
module top;
if (1)
    begin : correct_name
        initial $display("HI");
    end : incorrect_name
endmodule
EOF
Tests: Prefer single quotes for regex Replaces double quotes on problematic regex strings (mostly ones that have escape sequences that are easier to preserve in single quotes). Necessitates also changing single quotes to `.`, i.e match any. For some (mostly ones that only have a single escaped character, or were using `\.` to match a literal fullstop) keep the double quotes and fix the regex instead. 2025-10-06 03:22:18 +02:00			`logger -expect error 'Begin label \(correct_name\) and end label \(incorrect_name\) don.t match\.' 1`
sv: fix up end label checking - disallow [gen]blocks with an end label but not begin label - check validity of module end label - fix memory leak of package name and end label - fix memory leak of module end label 2021-06-14 21:32:01 +02:00			`read_verilog -sv <<EOF`
			`module top;`
			`if (1)`
			`begin : correct_name`
			`initial $display("HI");`
			`end : incorrect_name`
			`endmodule`
			`EOF`