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yosys/tests/sim/assume_x_first_step.ys

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Assume x values for missing signal data in FST Co-authored-by: Miodrag Milanovic <mmicko@gmail.com> Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
2024-10-02 11:18:19 +02:00
read_verilog simple_assign.v
End of file fix
2026-06-23 07:23:41 +02:00
sim -r simple_assign.vcd -scope simple_assign