2019-09-23 11:12:02 +02:00
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read_verilog add_sub.v
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hierarchy -top top
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equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 10 t:AL_MAP_ADDER
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select -assert-count 4 t:AL_MAP_LUT1
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2019-10-04 11:09:59 +02:00
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select -assert-none t:AL_MAP_LUT1 t:AL_MAP_ADDER %% t:* %D
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