ast_range_err_message/tests/errors/syntax_err09.v

module a(input wire x = 1'b0);
endmodule
Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique, 2018-10-25 02:37:56 +03:00			`module a(input wire x = 1'b0);`
			`endmodule`