scl-cache-dir/docs/source/code_examples/opt/opt_muxtree.ys

read_verilog <<EOT

module uut(
    input a, b, c, d,
    output y
);
    assign y = a ? (a ? b : c) : d;
endmodule

EOT

copy uut after
opt_muxtree after
clean

show -format dot -prefix opt_muxtree_full -notitle -color cornflowerblue uut
Docs: working on opt page 2024-01-17 11:00:42 +13:00			`read_verilog <<EOT`

			`module uut(`
			`input a, b, c, d,`
			`output y`
Remove trailing whitespaces 2026-06-23 07:24:59 +02:00			`);`
Docs: working on opt page 2024-01-17 11:00:42 +13:00			`assign y = a ? (a ? b : c) : d;`
			`endmodule`

			`EOT`

			`copy uut after`
			`opt_muxtree after`
			`clean`

			`show -format dot -prefix opt_muxtree_full -notitle -color cornflowerblue uut`