yosys/docs/source/code_examples/show/cmos.ys

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# pitfall
read_verilog cmos.v
prep -top cmos_demo
techmap
2026-06-23 07:24:59 +02:00
abc -liberty ../intro/mycells.lib;;
show -format dot -prefix cmos_00
# reset
design -reset
# fixed output
read_verilog cmos.v
prep -top cmos_demo
techmap
splitnets -ports
2026-06-23 07:24:59 +02:00
abc -liberty ../intro/mycells.lib;;
show -lib ../intro/mycells.v -format dot -prefix cmos_01