driver/docs/source/code_examples/axis/axis_test.ys

read_verilog -sv axis_master.v axis_test.v
hierarchy -top axis_test

proc; flatten;;
sat -seq 50 -prove-asserts
Progress in presentation 2014-06-21 16:33:33 +02:00			`read_verilog -sv axis_master.v axis_test.v`
			`hierarchy -top axis_test`

			`proc; flatten;;`
docs: moving code examples 2023-11-14 12:55:39 +13:00			`sat -seq 50 -prove-asserts`