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yosys/techlibs/xilinx/Makefile.inc

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Added synth_xilinx command
2013-10-27 09:33:47 +01:00
OBJS += techlibs/xilinx/synth_xilinx.o
xilinx: Add xilinx_dffopt pass (#1557)
2019-12-18 13:42:26 +01:00
OBJS += techlibs/xilinx/xilinx_dffopt.o
Added synth_xilinx command
2013-10-27 09:33:47 +01:00
xilinx: Use `memory_libmap` pass.
2022-02-06 10:10:40 +01:00
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_sim.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_xtra.v))
Added support for initialized xilinx brams
2015-04-06 17:07:10 +02:00
xilinx: Use `memory_libmap` pass.
2022-02-06 10:10:40 +01:00
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_xcv.txt))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_xcv_map.v))
Added support for initialized xilinx brams
2015-04-06 17:07:10 +02:00
xilinx: Use `memory_libmap` pass.
2022-02-06 10:10:40 +01:00
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_xc5v.txt))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_xcu.txt))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_xc5v_map.v))
Added support for initialized xilinx brams
2015-04-06 17:07:10 +02:00
xilinx: Use `memory_libmap` pass.
2022-02-06 10:10:40 +01:00
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xcv.txt))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xcv_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_defs.vh))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xc2v.txt))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xc2v_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xc3sda.txt))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xc3sda_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xc4v.txt))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xc4v_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xc5v_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xc6v_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xcu_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/urams.txt))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/urams_map.v))
Added support for initialized xilinx brams
2015-04-06 17:07:10 +02:00
Various cleanups in xilinx techlib
2015-01-18 19:43:54 +01:00
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
xilinx: Use dfflegalize.
2020-06-23 18:51:51 +02:00
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
Changes required for VPR place and route synth_xilinx. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-01 20:21:07 +01:00
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
Revert "Remove wide mux inference" This reverts commit 738fdfe8f55e18ac7f315cd68c117eae370004ca.
2019-06-14 21:50:24 +02:00
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v))
xilinx: Support multiplier mapping for all families. This supports several older families that are not yet supported for actual logic synthesis — the intention is to add them soon.
2019-10-08 19:00:30 +02:00
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc3s_mult_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc3sda_dsp_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_dsp_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc4v_dsp_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc5v_dsp_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_dsp_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_dsp_map.v))
install *_nowide.lut files
2019-06-30 04:37:04 +02:00
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 20:04:10 +02:00
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_model.v))
pmgen: Move passes out of pmgen folder - Techlib pmgens are now in relevant techlibs/*. - `peepopt` pmgens are now in passes/opt. - `test_pmgen` is still in passes/pmgen. - Update `Makefile.inc` and `.gitignore` file(s) to match new `*_pm.h` location, as well as the `#include`s. - Change default `%_pm.h` make target to `techlibs/%_pm.h` and move it to the top level Makefile. - Update pmgen target to use `$(notdir $*)` (where `$*` is the part of the file name that matched the '%' in the target) instead of `$(subst _pm.h,,$(notdir $@))`.
2025-01-31 03:06:09 +01:00
OBJS += techlibs/xilinx/xilinx_dsp.o
GENFILES += techlibs/xilinx/xilinx_dsp_pm.h
GENFILES += techlibs/xilinx/xilinx_dsp48a_pm.h
GENFILES += techlibs/xilinx/xilinx_dsp_CREG_pm.h
GENFILES += techlibs/xilinx/xilinx_dsp_cascade_pm.h
techlibs/xilinx/xilinx_dsp.o: techlibs/xilinx/xilinx_dsp_pm.h techlibs/xilinx/xilinx_dsp48a_pm.h techlibs/xilinx/xilinx_dsp_CREG_pm.h techlibs/xilinx/xilinx_dsp_cascade_pm.h
$(eval $(call add_extra_objs,techlibs/xilinx/xilinx_dsp_pm.h))
$(eval $(call add_extra_objs,techlibs/xilinx/xilinx_dsp48a_pm.h))
$(eval $(call add_extra_objs,techlibs/xilinx/xilinx_dsp_CREG_pm.h))
$(eval $(call add_extra_objs,techlibs/xilinx/xilinx_dsp_cascade_pm.h))
OBJS += techlibs/xilinx/xilinx_srl.o
GENFILES += techlibs/xilinx/xilinx_srl_pm.h
techlibs/xilinx/xilinx_srl.o: techlibs/xilinx/xilinx_srl_pm.h
$(eval $(call add_extra_objs,techlibs/xilinx/xilinx_srl_pm.h))