mirror of https://github.com/YosysHQ/yosys.git
16 lines
303 B
VHDL
16 lines
303 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity top is
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Port (
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a : in STD_LOGIC_VECTOR(3 downto 0);
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b : in STD_LOGIC_VECTOR(3 downto 0);
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y : out STD_LOGIC_VECTOR(3 downto 0)
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);
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end top;
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architecture Behavioral of top is
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begin
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y <= a nor b;
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end Behavioral;
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