mirror of https://github.com/YosysHQ/yosys.git
11 lines
234 B
Plaintext
11 lines
234 B
Plaintext
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read_verilog -sv <<EOF
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module thing(input [2:0] in, output reg [2:0] out);
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assign out = in;
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endmodule
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EOF
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select -assert-count 0 t:$eq
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fminit -set out 1'b1
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select -assert-count 1 t:$eq
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select -assert-count 1 t:$eq r:A_WIDTH=1 %i
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