mirror of https://github.com/YosysHQ/yosys.git
9 lines
171 B
Verilog
9 lines
171 B
Verilog
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module m(input a, output y1, output y2);
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assign y1 = a;
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assign y2 = a;
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endmodule
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module top(input a, output y2, output y1);
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m inst(.a(a), .y1(y1), .y2(y2));
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endmodule
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