mirror of https://github.com/YosysHQ/yosys.git
24 lines
372 B
Plaintext
24 lines
372 B
Plaintext
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read_verilog <<EOF
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module tag_2x4(
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input R0_clk,
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input W0_clk,
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output x,
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);
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assign x = !W0_clk;
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endmodule
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module top(input clock, output x, output flag);
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tag_2x4 tag_ext(
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.R0_clk (clock),
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.W0_clk (clock),
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.x (x)
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);
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assign flag = x ^ clock;
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endmodule
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EOF
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hierarchy -top top
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opt_hier
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flatten
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sat -verify -prove flag 1
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