yosys/tests/liberty/semicolextra.lib.verilogsim.ok

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2024-08-13 18:36:31 +02:00
module DFF (D, CK, Q);
reg IQ, IQN;
input D;
input CK;
output Q;
always @(posedge CK) begin
// "D"
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IQ <= D;
IQN <= ~(D);
end
endmodule