mirror of https://github.com/YosysHQ/yosys.git
12 lines
139 B
Plaintext
12 lines
139 B
Plaintext
|
read_verilog << EOF
|
||
|
|
module top(...);
|
||
|
|
input wire [31:0] A;
|
||
|
|
output wire [31:0] P;
|
||
|
|
|
||
|
|
assign P = A * 32'h12300000;
|
||
|
|
|
||
|
|
endmodule
|
||
|
|
EOF
|
||
|
|
|
||
|
|
synth_xilinx
|