2020-07-26 20:28:10 +02:00
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read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 10 sync_ram_sdp
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2022-07-11 02:31:38 +02:00
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synth_intel_alm -top sync_ram_sdp -family cyclonev -noiopad -noclkbuf
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2020-07-26 20:28:10 +02:00
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cd sync_ram_sdp
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2022-03-09 17:40:32 +01:00
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select -assert-count 1 t:MISTRAL_NOT
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2020-07-26 20:28:10 +02:00
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select -assert-count 1 t:MISTRAL_M10K
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2022-03-09 17:40:32 +01:00
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select -assert-none t:MISTRAL_NOT t:MISTRAL_M10K %% t:* %D
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2024-05-03 12:16:34 +02:00
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