2019-10-18 12:19:59 +02:00
|
|
|
read_verilog ../common/mul.v
|
2019-08-21 20:52:07 +02:00
|
|
|
hierarchy -top top
|
2020-01-01 03:40:11 +01:00
|
|
|
equiv_opt -assert -multiclock -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
|
2019-08-21 20:52:07 +02:00
|
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
|
|
|
cd top # Constrain all select calls below inside the top module
|
2019-08-22 21:17:25 +02:00
|
|
|
select -assert-count 1 t:SB_MAC16
|
|
|
|
|
select -assert-none t:SB_MAC16 %% t:* %D
|
